D ts e t
aa h e
R c e t r lc r nc
o h se Ee to is
Ma u a t r dCo o e t
n fc u e
mp n n s
R c e tr b a d d c mp n ns ae
o h se rn e
o oet r
ma ua trd u ig ete dewaes
n fcue sn i r i/ fr
h
p rh s d f m te oiia s p l r
uc a e r
o h r n l u pi s
g
e
o R c e tr waes rce td f m
r o h se
fr e rae r
o
te oiia I. Al rce t n ae
h
r nl P
g
l e rai s r
o
d n wi tea p o a o teOC
o e t h p rv l f h
h
M.
P r aetse u igoiia fcoy
at r e td sn r n la tr
s
g
ts p o rmso R c e tr e eo e
e t rga
r o h se d v lp d
ts s lt n t g aa te p o u t
e t oui s o u rne
o
rd c
me t o e c e teOC d t s e t
es r x e d h
M aa h e.
Qu l yOv riw
ai
t
e ve
• IO- 0 1
S 90
•A 92 cr ct n
S 1 0 et ai
i
o
• Qu l e Ma ua trr Ls (
ai d
n fcues it QML MI- R -
) LP F
385
53
•C a sQ Mitr
ls
lay
i
•C a sVS a eL v l
ls
p c ee
• Qu l e S p l r Ls o D sr uos( L )
ai d u pi s it f it b tr QS D
e
i
•R c e trsacic l u pir oD A a d
o h se i
r ia s p l t L n
t
e
me t aln u t a dD A sa d r s
es lid sr n L tn ad .
y
R c e tr lcrnc , L i c mmi e t
o h se Ee t is L C s o
o
tdo
t
s p ligp o u t ta s t f c so r x e t-
u pyn rd cs h t ai y u tme e p ca
s
t n fr u lya daee u loto eoiial
i s o q ai n r q a t h s r n l
o
t
g
y
s p l db id sr ma ua trr.
u pi
e yn ut
y n fcues
T eoiia ma ua trr d ts e t c o a yn ti d c me t e e t tep r r n e
h r n l n fcue’ aa h e a c mp n ig hs o u n r cs h ef ma c
g
s
o
a ds e ic t n o teR c e tr n fcue v rino ti d vc . o h se Ee t n
n p c ai s f h o h se ma ua trd eso f hs e ie R c e tr lcr -
o
o
isg aa te tep r r n eo i s mio d co p o u t t teoiia OE s e ic -
c u rne s h ef ma c ft e c n u tr rd cs o h r n l M p c a
o
s
g
t n .T pc lv le aefr eee c p r o e o l. eti mii m o ma i m rt g
i s ‘y ia’ au s r o rfrn e up s s ny C r n nmu
o
a
r xmu ai s
n
ma b b s do p o u t h rceiain d sg , i lt n o s mpetsig
y e a e n rd c c aa tr t , e in smuai , r a l e t .
z o
o
n
© 2 1 R cetr l t n s LC Al i t R sre 0 1 2 1
0 3 ohs E cr i , L . lRg s eevd 7 1 0 3
e e oc
h
T l r m r, l s v iw wrcl . m
o e n oe p ae it w . e c o
a
e
s
o ec
Low Capacitance, Triple/Quad SPDT
±15 V/+12 V
i
CMOS™ Switches
ADG1233/ADG1234
FEATURES
1.5 pF off capacitance
0.5 pC charge injection
33 V supply range
120 Ω on resistance
Fully specified at ±15 V/+12 V
3 V logic-compatible inputs
Rail-to-rail operation
Break-before-make switching action
16-lead TSSOP, 20-lead TSSOP, and 4 mm × 4 mm LFCSP
Typical power consumption (<0.03 μW)
FUNCTIONAL BLOCK DIAGRAMS
ADG1233
S1A
D1
S1B
S3B
D3
S3A
S2B
D2
S2A
LOGIC
IN1 IN2 IN3 EN
SWITCHES SHOWN FOR A LOGIC 1 INPUT
Audio and video routing
Automatic test equipment
Data acquisition systems
Battery-powered systems
Sample-and-hold systems
Communication systems
Figure 1.
ADG1234
S1A
D1
S1B
S4A
D4
S4B
GENERAL DESCRIPTION
The ADG1233 and ADG1234 are monolithic
iCMOS
analog
switches comprising three independently selectable single-pole,
double throw SPDT switches and four independently selectable
SPDT switches, respectively.
All channels exhibit break-before-make switching action
preventing momentary shorting when switching channels.
An EN input on the ADG1233 and ADG1234 is used to
enable or disable the device. When disabled, all channels are
switched off.
The
iCMOS
(industrial-CMOS) modular manufacturing process
combines a high voltage complementary metal-oxide semi-
conductor (CMOS) and bipolar technologies. It enables the
development of a wide range of high performance analog ICs
capable of 33 V operation in a footprint that no other generation of
high voltage parts has been able to achieve. Unlike analog ICs
using conventional CMOS processes,
iCMOS
components can
tolerate high supply voltages while providing increased perfor-
mance, dramatically lowered power consumption, and reduced
package size.
The ultralow capacitance and charge injection of these multiplexers
make them ideal solutions for data acquisition and sample-and-
hold applications, where low glitch and fast settling are required.
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
S2B
D2
S2A
LOGIC
S3B
D3
S3A
IN1 IN2 IN3 IN4 EN
SWITCHES SHOWN FOR A LOGIC 1 INPUT
Figure 2.
Fast switching speed coupled with high signal bandwidth make the
parts suitable for video signal switching.
iCMOS
construction
ensures ultralow power dissipation, making the parts ideally
suited for portable and battery-powered instruments.
PRODUCT HIGHLIGHTS
1.
2.
3.
4.
1.5 pF off capacitance (±15 V supply).
0.5 pC charge injection.
3 V logic-compatible digital input, V
IH
= 2.0 V, V
IL
= 0.8 V.
16-lead TSSOP, 20-lead TSSOP, and 4 mm × 4 mm LFCSP.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2006–2009 Analog Devices, Inc. All rights reserved.
05743-038
05743-001
APPLICATIONS
ADG1233/ADG1234
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagrams ............................................................. 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Dual Supply ................................................................................... 3
Single Supply ................................................................................. 5
Absolute Maximum Ratings ............................................................7
ESD Caution...................................................................................7
Pin Configurations and Function Descriptions ............................8
Terminology .......................................................................................9
Typical Performance Characteristics ........................................... 10
Test Circuits ..................................................................................... 13
Outline Dimensions ....................................................................... 15
Ordering Guide .......................................................................... 16
REVISION HISTORY
2/09—Rev.
A to Rev. B
Change to I
DD
Parameter, Table 1 ................................................... 4
Change to I
DD
Parameter, Table 2 ................................................... 6
Updated Outline Dimensions ....................................................... 16
8/06—Rev. 0 to Rev. A
Updated Format…………………………….….…………Universal
Changes to Table 1…………………………………………….…...3
Changes to Table 2………………………………………………....4
Changes to Figure 11……………………..………………………10
Changes to Figure 12……………………………………………..11
1/06—Revision 0: Initial Version
Rev. B | Page 2 of 16
ADG1233/ADG1234
SPECIFICATIONS
DUAL SUPPLY
V
DD
= +15 V ± 10%, V
SS
= −15 V ± 10%, GND = 0 V, unless otherwise noted.
Table 1.
Parameter
ANALOG SWITCH
Analog Signal Range
On Resistance (R
ON
)
On Resistance Match Between
Channels (∆R
ON
)
On Resistance Flatness (R
FLAT (ON)
)
LEAKAGE CURRENTS
Source Off Leakage I
S
(Off )
Drain Off Leakage I
D
(Off )
+25°C
Y Version
1
−40°C to +85°C −40°C to +125°C
V
SS
to V
DD
120
190
3.5
6
20
60
±0.02
±0.1
±0.02
±0.1
±0.02
±0.2
230
260
Unit
V
Ω typ
Ω max
Ω typ
Ω max
Ω typ
Ω max
nA typ
nA max
nA typ
nA max
nA typ
nA max
V min
V max
μA typ
μA max
pF typ
ns typ
ns max
ns typ
ns min
ns typ
ns max
ns typ
ns max
pC typ
dB typ
dB typ
% typ
MHz typ
pF typ
pF max
pF typ
pF max
pF typ
pF max
Rev. B | Page 3 of 16
Test Conditions/Comments
V
S
= ±10 V, I
S
= −1 mA; see Figure 24
V
DD
= +13.5 V, V
SS
= −13.5 V
V
S
= ±10 V, I
S
= −1 mA
10
72
12
79
V
S
= −5 V, 0 V, +5 V; I
S
= −1 mA
V
DD
= +16.5 V, V
SS
= −16.5 V
V
D
= ±10 V, V
S
= −10 V; see Figure 25
V
S
= 1 V/10 V, V
D
= 10 V/1 V;
see Figure 25
V
S
= V
D
= ±10 V; see Figure 26
±0.6
±1
±0.6
±0.6
±1
±1
2.0
0.8
Channel On Leakage I
D,
I
S
(On)
DIGITAL INPUTS
Input High Voltage, V
INH
Input Low Voltage, V
INL
Input Current
I
INL
or I
INH
Digital Input Capacitance, C
IN
DYNAMIC CHARACTERISTICS
2
t
TRANSITION
t
BBM
t
ON
(EN)
t
OFF
(EN)
Charge Injection
Off Isolation
Channel-to-Channel Crosstalk
Total Harmonic Distortion, THD + N
−3 dB Bandwidth
C
S
(Off )
C
D
(Off )
C
D
, C
S
(On)
±0.005
±0.1
3
110
130
25
120
140
40
45
0.5
−80
−85
0.14
900
1.5
1.7
1.6
1.8
3.5
4
V
IN
= V
INL
or V
INH
150
170
10
170
55
195
60
R
L
= 300 Ω, C
L
= 35 pF
V
S
= 10 V; see Figure 27
R
L
= 300 Ω, C
L
= 35 pF
V
S1
= V
S2
= +10 V; see Figure 28
R
L
= 300 Ω, C
L
= 35 pF
V
S
= 10 V; see Figure 29
R
L
= 300 Ω, C
L
= 35 pF
V
S
= 10 V; see Figure 29
V
S
= 0 V, R
S
= 0 Ω, C
L
= 1 nF;
see Figure 30
R
L
= 50 Ω, C
L
= 5 pF, f = 1 MHz; see
Figure 31
R
L
= 50 Ω, C
L
= 5 pF, f = 1 MHz;
see Figure 33
R
L
= 10 kΩ, 5 V rms, f = 20 Hz to
20
kHz; see Figure 34
R
L
= 50 Ω, C
L
= 5 pF; see Figure 32
f = 1 MHz; V
S
= 0 V
f = 1 MHz; V
S
= 0 V
f = 1 MHz; V
S
= 0 V
f = 1 MHz; V
S
= 0 V
f = 1 MHz; V
S
= 0 V
f = 1 MHz; V
S
= 0 V
ADG1233/ADG1234
Parameter
POWER REQUIREMENTS
I
DD
I
DD
I
SS
I
SS
V
DD
/V
SS
1
2
+25°C
0.002
Y Version
1
−40°C to +85°C −40°C to +125°C
Unit
μA typ
μA max
μA typ
μA max
μA typ
μA max
μA typ
μA max
V min/max
Test Conditions/Comments
V
DD
= +16.5 V, V
SS
= −16.5 V
Digital inputs = 0 V or V
DD
Digital inputs = 5 V
Digital inputs = 0 V or V
DD
Digital inputs = 5 V
GND = 0 V
1.0
260
475
0.002
1.0
0.002
1.0
±5/±16.5
Temperature range for the Y version: −40°C to +125°C.
Guaranteed by design, not subject to production test.
Rev. B | Page 4 of 16
嵌入式系统
