Data Sheet
FEATURES
9.5 Ω R
ON
, ±15 V/+12 V/±5 V
iCMOS,
Serially-Controlled Octal SPST Switches
ADG1414
FUNCTIONAL BLOCK DIAGRAM
ADG1414
S1
S2
S3
S4
S5
S6
S7
S8
INPUT SHIFT
REGISTER
D1
D2
D3
D4
D5
D6
D7
D8
SPI interface
Supports daisy-chain mode
9.5 Ω on resistance at 25°C and ±15 V dual supply
1.6 Ω on-resistance flatness at 25°C and ±15 V dual supply
Fully specified at ±15 V, +12 V, ±5 V
3 V logic-compatible inputs
Rail-to-rail operation
24-lead TSSOP and 24-lead, 4 mm × 4 mm LFCSP
APPLICATIONS
Automatic test equipment
Data acquisition systems
Battery-powered systems
Sample-and-hold systems
Audio signal routing
Video signal routing
Communication systems
SDO
08497-001
SCLK DIN SYNC
RESET/V
L
Figure 1.
GENERAL DESCRIPTION
The
ADG1414
is a monolithic complementary metal-oxide
semiconductor (CMOS) device containing eight independently
selectable switches designed on an industrial CMOS (iCMOS®)
process.
iCMOS
is a modular manufacturing process combining
high voltage CMOS and bipolar technologies.
iCMOS
components
can tolerate high supply voltages while providing increased perfor-
mance, dramatically lower power consumption, and reduce the
package size.
The
ADG1414
is a set of octal, single-pole, single-throw (SPST)
switches controlled via a 3-wire serial interface. On resistance is
matched closely between switches and is very flat over the full
signal range. Each switch conducts equally well in both directions
and the input signal range extends to the supplies.
Data is written to these devices in the form of eight bits; each
bit corresponds to one channel.
The
ADG1414
uses a versatile 3-wire serial interface that
operates at clock rates of up to 50 MHz and is compatible with
standard SPI, QSPI™, MICROWIRE™, and DSP interface
standards. The output of the shift register, SDO, enables a
number of these devices to be daisy chained.
At power-up, all switches are in the off condition, and the
internal registers contain all zeros.
PRODUCT HIGHLIGHTS
1.
2.
3.
4.
50 MHz serial interface.
9.5 Ω on resistance.
1.6 Ω on-resistance flatness.
24-lead TSSOP and 4 mm × 4 mm LFCSP packages.
Rev. B
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ADG1414
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Functional Block Diagram .............................................................. 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
±15 V Dual Supply ....................................................................... 3
12 V Single Supply ........................................................................ 4
±5 V Dual Supply ......................................................................... 6
Continuous Current per Channel .............................................. 7
Timing Characteristics ................................................................ 8
Absolute Maximum Ratings ............................................................ 9
Thermal Resistance ...................................................................... 9
Data Sheet
ESD Caution...................................................................................9
Pin Configurations and Function Descriptions ......................... 10
Typical Performance Characteristics ........................................... 12
Test Circuits..................................................................................... 15
Terminology .................................................................................... 17
Theory of Operation ...................................................................... 18
Serial Interface ............................................................................ 18
Input Shift Register .................................................................... 18
Power-On Reset .......................................................................... 18
Daisy Chaining ........................................................................... 18
Outline Dimensions ....................................................................... 19
Ordering Guide .......................................................................... 19
REVISION HISTORY
11/15—Rev. A to Rev. B
Changes to V
DD
/V
SS
Parameter, Table 2 ......................................... 5
Updated Outline Dimensions ....................................................... 19
1/13—Rev. 0 to Rev. A
Changes to RESET/V
L
Pin Description Column, Table 9 ......... 11
Changes to Power-On Reset Section ............................................ 19
Updated Outline Dimensions ....................................................... 20
10/09—Revision 0: Initial Version
Rev. B | Page 2 of 19
Data Sheet
SPECIFICATIONS
±15 V DUAL SUPPLY
V
DD
= 15 V ± 10%, V
SS
= −15 V ± 10%, V
L
= 2.7 V to 5.5 V, GND = 0 V, unless otherwise noted.
Table 1.
Parameter
ANALOG SWITCH
Analog Signal Range
On Resistance (R
ON
)
+25°C
−40°C to
+85°C
−40°C to
+125°C
V
SS
to V
DD
9.5
11.5
0.55
1
1.6
1.9
LEAKAGE CURRENTS
Source Off Leakage, I
S
(Off )
Drain Off Leakage, I
D
(Off )
Channel On Leakage, I
D
, I
S
(On)
DIGITAL INPUTS
Input High Voltage (V
INH
)
Input Low Voltage (V
INL
)
Input Current
Digital Input Capacitance (C
IN
)
LOGIC OUTPUTS (SDO)
Output Low Voltage (V
OL
)
1
High Impedance Leakage Current
High Impedance Output Capacitance
DYNAMIC CHARACTERISTICS
1
t
ON
t
OFF
Charge Injection
Off Isolation
Channel-to-Channel Crosstalk
Total Harmonic Distortion (THD + N)
−3 dB Bandwidth
Insertion Loss
C
D
, C
S
(Off )
C
D
, C
S
(On)
1
ADG1414
Unit
V
Ω typ
Ω max
Ω typ
Ω max
Ω typ
Ω max
Test Conditions/Comments
V
DD
= +13.5 V, V
SS
= −13.5 V, V
S
= ±10 V,
I
S
= −10 mA; see Figure 23
V
DD
= +13.5 V, V
SS
= −13.5 V, V
S
= ±10 V,
I
S
= −10 mA
V
DD
= +13.5 V, V
SS
= −13.5 V, V
S
= ±10 V,
I
S
= −10 mA
V
DD
= +16.5 V, V
SS
= −16.5 V
14
16
On-Resistance Match Between Channels (ΔR
ON
)
1.5
1.7
On-Resistance Flatness (R
FLAT (ON)
)
2.15
2.3
±0.05
±0.15
±0.05
±0.15
±0.1
±0.3
±1
±1
±2
±2
±2
±4
2.0
0.8
±0.001
±0.1
4
0.4
0.6
0.001
±1
4
75
93
25
35
10
−73
−75
0.05
256
0.55
8
32
nA typ
nA max
nA typ
nA max
nA typ
nA max
V min
V max
µA typ
µA max
pF typ
V max
V max
µA typ
µA max
pF typ
ns typ
ns max
ns typ
ns max
pC typ
dB typ
dB typ
% typ
MHz typ
dB typ
pF typ
pF typ
V
S
= ±10 V, V
D
=
∓
10 V; see Figure 24
V
S
= ±10 V, V
D
=
∓
10 V; see Figure 24
V
S
= V
D
= ±10 V; see Figure 25
V
IN
= V
GND
or V
L
I
SINK
= 3 mA
I
SINK
= 6 mA
110
35
120
35
R
L
= 100 Ω, C
L
= 35 pF
V
S
= 10 V; see Figure 30
R
L
= 100 Ω, C
L
= 35 pF
V
S
= 10 V; see Figure 30
V
S
= 0 V, R
S
= 0 Ω, C
L
= 1 nF; see Figure 31
R
L
= 50 Ω, C
L
= 5 pF, f = 1 MHz; see Figure 26
R
L
= 50 Ω, C
L
= 5 pF, f = 1 MHz; see Figure 27
R
L
= 110 Ω, 15 V p-p, f = 20 Hz to 20 kHz;
see Figure 29
R
L
= 50 Ω, C
L
= 5 pF; see Figure 28
R
L
= 50 Ω, C
L
= 5 pF, f = 1 MHz; see Figure 28
f = 1 MHz
f = 1 MHz
Rev. B | Page 3 of 19
ADG1414
Parameter
POWER REQUIREMENTS
I
DD
I
L
Inactive
I
L
Active at 30 MHz
I
L
Active at 50 MHz
I
SS
V
DD
/V
SS
1
Data Sheet
+25°C
0.001
1
0.3
1
0.26
0.3
0.42
0.5
0.001
1
±4.5/±16.5
0.55
0.35
−40°C to
+85°C
−40°C to
+125°C
Unit
µA typ
µA max
µA typ
µA max
mA typ
mA max
mA typ
mA max
µA typ
µA max
V min/max
Test Conditions/Comments
V
DD
= +16.5 V, V
SS
= −16.5 V
Digital inputs = 0 V or V
L
Digital inputs = 0 V or V
L
Digital inputs toggle between 0 V and V
L
Digital inputs toggle between 0 V and V
L
Digital inputs = 0 V or V
L
Guaranteed by design, not subject to production test.
12 V SINGLE SUPPLY
V
DD
= 12 V ± 10%, V
SS
= 0 V, V
L
= 2.7 V to 5.5 V, GND = 0 V, unless otherwise noted.
Table 2.
Parameter
ANALOG SWITCH
Analog Signal Range
On Resistance (R
ON
)
+25°C
−40°C to
+85°C
−40°C to
+125°C
0 to V
DD
18
21.5
0.55
1.2
5
6
LEAKAGE CURRENTS
Source Off Leakage, I
S
(Off )
Drain Off Leakage, I
D
(Off )
Channel On Leakage, I
D
, I
S
(On)
DIGITAL INPUTS
Input High Voltage (V
INH
)
Input Low Voltage (V
INL
)
Input Current
Digital Input Capacitance (C
IN
)
LOGIC OUTPUTS (SDO)
Output Low Voltage (V
OL
)
1
High Impedance Leakage Current
High Impedance Output Capacitance
1
±0.02
±0.15
±0.02
±0.15
±0.05
±0.3
26
28.5
Unit
V
Ω typ
Ω max
Ω typ
Ω max
Ω typ
Ω max
nA typ
nA max
nA typ
nA max
nA typ
nA max
V min
V max
µA typ
µA max
pF typ
V max
V max
µA max
pF typ
V
DD
= 10.8 V
V
S
= 1 V/10 V, V
D
= 10 V/1 V; see Figure 24
V
S
= 1 V/10 V, V
D
= 10 V/1 V; see Figure 24
V
S
= V
D
= 1 V or 10 V; see Figure 25
Test Conditions/Comments
V
DD
= 10.8 V, V
SS
= 0 V; V
S
= 0 V to 10 V,
I
S
= −10 mA; see Figure 23
V
DD
= 10.8 V, V
SS
= 0 V; V
S
= 0 V to 10 V,
I
S
= −10 mA
V
DD
= 10.8 V, V
SS
= 0 V; V
S
= 0 V to 10 V,
I
S
= −10 mA
On-Resistance Match Between Channels (ΔR
ON
)
1.6
1.8
On-Resistance Flatness (R
FLAT (ON)
)
6.9
7.3
±1
±1
±2
±2
±2
±4
2.0
0.8
±0.001
±0.1
4
0.4
0.6
±1
4
V
IN
= V
GND
or V
L
I
SINK
= 3 mA
I
SINK
= 6 mA
Rev. B | Page 4 of 19
Data Sheet
Parameter
DYNAMIC CHARACTERISTICS
1
t
ON
t
OFF
Charge Injection
Off Isolation
Channel-to-Channel Crosstalk
−3 dB Bandwidth
Insertion Loss
C
D
, C
S
(Off )
C
D
, C
S
(On)
POWER REQUIREMENTS
I
DD
I
L
Inactive
I
L
Active at 30 MHz
I
L
Active at 50 MHz
I
SS
V
DD
/V
SS
1
ADG1414
+25°C
145
185
35
45
8
−70
−75
240
1.15
12
33
0.001
1
0.3
1
0.26
0.3
0.42
0.5
0.001
1
5/16.5
0.55
0.35
−40°C to
+85°C
−40°C to
+125°C
Unit
ns typ
ns max
ns typ
ns max
pC typ
dB typ
dB typ
MHz typ
dB typ
pF typ
pF typ
µA typ
µA max
µA typ
µA max
mA typ
mA max
mA typ
mA max
µA typ
µA max
V min/max
Test Conditions/Comments
R
L
= 100 Ω, C
L
= 35 pF
V
S
= 8 V; see Figure 30
R
L
= 100 Ω, C
L
= 35 pF
V
S
= 8 V; see Figure 30
V
S
= 6 V, R
S
= 0 Ω, C
L
= 1 nF; see Figure 31
R
L
= 50 Ω, C
L
= 5 pF, f = 1 MHz;
see Figure 26
R
L
= 50 Ω, C
L
= 5 pF, f = 1 MHz;
see Figure 27
R
L
= 50 Ω, C
L
= 5 pF; see Figure 28
R
L
= 50 Ω, C
L
= 5 pF, f = 1 MHz;
see Figure 28
f = 1 MHz
f = 1 MHz
V
DD
= +13.2 V
Digital inputs = 0 V or V
L
Digital inputs = 0 V or V
L
Digital inputs toggle between 0 V and V
L
Digital inputs toggle between 0 V and V
L
Digital inputs = 0 V or V
L
220
46
240
46
Guaranteed by design, not subject to production test.
Rev. B | Page 5 of 19
DSP 与 ARM 处理器
