Data Sheet
FEATURES
44 V supply maximum rating
±15 V analog signal range
Low R
ON
: 115 Ω maximum
Low leakage: 0.5 nA typical
Break-before-make switching
Single supply operation possible
Extended plastic temperature range: −40°C to +85°C
TTL/CMOS compatible
Available in 16-lead PDIP/SOIC and 20-pead PLCC packages
Pin compatible to DG211/DG212
LC
2
MOS
Quad SPST Switches
ADG211A/ADG212A
FUNCTIONAL BLOCK DIAGRAM
ADG211A
S1
IN1
D1
S2
IN2
D2
S3
IN3
D3
S4
IN4
D4
NOTES
1. SWITCHES SHOWN FOR A LOGIC 1 INPUT.
10950-001
10950-002
Figure 1.
ADG212A
S1
IN1
D1
S2
IN2
D2
S3
IN3
D3
S4
IN4
D4
NOTES
1. SWITCHES SHOWN FOR A LOGIC 1 INPUT.
Figure 2.
GENERAL DESCRIPTION
The
ADG211A
and
ADG212A
are monolithic CMOS devices
comprising four independently selectable switches. They are
designed on an enhanced LC
2
MOS process, which gives an
increased signal handling capability of ±15 V. These switches
also feature high switching speeds and low R
ON
.
The
ADG211A
and
ADG212A
consist of four SPST switches.
They differ only in that the digital control logic is inverted. In
multiplexer applications, all switches exhibit break-before-make
switching action when driven simultaneously. Inherent in the
design is low charge injection for minimum transients when
switching the digital inputs.
PRODUCT HIGHLIGHTS
1.
Extended Signal Range.
These switches are fabricated on an enhanced LC
2
MOS
process, resulting in high breakdown and an increased
analog signal range of ±15 V.
Single Supply Operation.
For applications where the analog signal is unipolar (0 V to
15 V), the switches can be operated from a single 15 V
supply.
Low Leakage.
Leakage currents in the range of 500 pA make these
switches suitable for high precision circuits. The added
feature of break-before-make allows for multiple outputs
to be tied together for multiplexer applications while
keeping leakage errors to a minimum.
2.
3.
Rev. C
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ADG211A/ADG212A
TABLE OF CONTENTS
Features .............................................................................................. 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Absolute Maximum Ratings............................................................ 4
Data Sheet
ESD Caution...................................................................................4
Pin Configurations and Function Descriptions ............................5
Typical Performance Characteristics ..............................................6
Terminology .......................................................................................9
Test Circuits ..................................................................................... 10
Outline Dimensions ....................................................................... 12
Ordering Guide .......................................................................... 13
REVISION HISTORY
10/12—Rev. B to Rev. C
Updated Format .................................................................. Universal
Added Pin Descriptions, Table 3 .................................................... 5
Moved Table 4 ................................................................................... 5
Changes to Figure 5, Figure 6, Figure 8, and Figure 9 ................. 6
Updated Outline Dimensions ....................................................... 13
Changes to Ordering Guide .......................................................... 14
9/02—Rev. A to Rev. B
Rev. C | Page 2 of 16
Data Sheet
SPECIFICATIONS
V
DD
= +15 V, V
SS
= −15 V, V
L
= 5 V, unless otherwise noted.
Table 1.
Parameter
ANALOG SWITCH
Analog Signal Range
R
ON
R
ON
vs. V
D
(V
S
)
R
ON
Drift
R
ON
Match
LEAKAGE CURRENTS
I
S
(Off )
Off Input Leakage
I
D
(Off )
Off Output Leakage
I
D
(On)
On Channel Leakage
DIGITAL CONTROL
V
INH
, Input High Voltage
V
INL
, Input Low Voltage
I
NL
or I
NH
C
IN
, Digital Input Capacitance
DYNAMIC CHARACTERISTICS
t
OPEN 1
t
ON1
t
OFF1
Off Isolation
Channel-to-Channel Crosstalk
C
S
(Off )
C
D
(Off )
C
S
, C
D
(On)
Q
INJ
, Charge Injection
POWER SUPPLY
I
DD
I
DD
I
SS
I
SS
I
L
1
ADG211A/ADG212A
Min
25°C
Typ
±15
Max
−40°C to +85°C
Min Typ Max
±15
Unit
V
Ω
%
%/°C
%
nA
nA
nA
nA
nA
nA
V
V
µA
pF
ns
ns
ns
dB
dB
pF
pF
pF
pC
mA
mA
mA
mA
mA
Test Conditions/Comments
115
20
0.5
5
0.5
5
0.5
5
0.5
5
2.4
175
−10 V ≤ V
S
≤ +10 V, I
DS
= 1 mA, see Figure 21
V
S
= 0 V, I
DS
= 1 mA
V
D
= ±14 V; V
S
=
14 V; see Figure 22
V
D
= ±14 V; V
S
=
14 V; see Figure 22
V
D
= V
S
= ±14 V; see Figure 23
100
100
200
TTL compatibility is independent of V
L
0.8
1
5
30
600
450
80
80
5
5
16
20
0.6
1
0.1
0.2
0.9
See Figure 24
See Figure 25
See Figure 25
V
S
= 10 V (p-p); f = 100 kHz;
R
L
= 75 Ω; see Figure 26
See Figure 27
R
S
= 0 Ω; C
L
= 1000 pF; V
S
= 0 V; see Figure 28
Digital inputs = V
INL
or V
INH
Sample tested at 25°C to ensure compliance.
Rev. C | Page 3 of 16
ADG211A/ADG212A
ABSOLUTE MAXIMUM RATINGS
T
A
= 25°C, unless otherwise stated.
Table 2.
Parameter
V
DD
to V
SS
V
DD
to GND
V
SS
to GND
V
L
to GND
Analog Inputs
1
Voltage at S, D
Continuous Current, S or D
Pulsed Current S or D
1 ms Duration, 10% Duty Cycle
Digital Inputs
1
Voltage at IN
Rating
44 V
25 V
−25 V
−0.3 V, 25 V
V
SS
− 0.3 V to V
DD
+ 0.3 V
30 mA
70 mA
V
SS
− 2 V to V
DD
+ 2 V or
20 mA, Whichever
Occurs First
470 mW
6 mW/°C
−40°C to +85°C
−65°C to +150°C
+300°C
Data Sheet
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
Power Dissipation (Any Package)
Up to +75°C
Derates above +75°C by
Operating Temperature
Storage Temperature Range
Lead Temperature (Soldering 10 sec)
1
Overvoltage at IN, S, or D will be clamped by diodes. Current should be
limited to the Maximum Rating listed in Table 2.
Rev. C | Page 4 of 16
Data Sheet
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
NIC
IN1
ADG211A/ADG212A
IN2
20
D1
3
2
1
19
18
S2
17
V
DD
16
NIC
15
V
L
14
S3
13
S1
4
5
6
7
8
9
PIN 1
INDENTFIER
IN1
1
D1
2
S1
3
V
SS 4
GND
5
S4
6
D4
7
IN4
8
16
IN2
V
SS
NIC
GND
S4
ADG211A/
ADG212A
TOP VIEW
(Not to Scale)
15
D2
14
S2
13
V
DD
12
V
L
11
S3
10950-003
ADG211A/
ADG212A
TOP VIEW
(Not to Scale)
11
12
10
NIC
IM3
IN4
D4
D3
D2
10
D3
9
IN3
NOTES
1. NIC = NO INTERNAL CONNECTION.
Figure 3. PDIP, SOIC Pin Configuration
Figure 4. PLCC Pin Configuration
Table 3. Pin Function Descriptions
PDIP, SOIC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Pin No.
PLCC
2
3
4
5
7
8
9
10
12
13
14
15
17
18
19
20
1, 6, 11, 16
Mnemonic
IN1
D1
S1
V
SS
GND
S4
D4
IN4
IN3
D3
S3
V
L
V
DD
S2
D2
IN2
NIC
Description
Logic Control Input.
Drain Terminal. Can be an input or output.
Source Terminal. Can be an input or output.
Most Negative Power Supply Potential.
Ground (0 V) Reference.
Source Terminal. Can be an input or output.
Drain Terminal. Can be an input or output.
Logic Control Input.
Logic Control Input.
Drain Terminal. Can be an input or output.
Source Terminal. Can be an input or output.
Logic Supply Voltage.
Most Positive Power Supply Potential.
Source Terminal. Can be an input or output.
Drain Terminal. Can be an input or output.
Logic Control Input.
No Internal Connection.
Table 4. Truth Table
ADG211A
In
0
1
ADG212A
In
1
0
Switch Condition
On
Off
Rev. C | Page 5 of 16
10950-004
FPGA/CPLD
