+3 V/+5 V/±5 V CMOS 4- and 8-Channel
Analog Multiplexers
ADG658/ADG659
FEATURES
±2 V to ±6 V dual supply
2 V to 12 V single supply
Automotive temperature range −40°C to +125°C
<0.1 nA leakage currents
45 Ω on resistance over full signal range
Rail-to-rail switching operation
Single 8-to-1 multiplexer ADG658
Differential 4-to-1 multiplexer ADG659
16-lead LFCSP/TSSOP/QSOP packages
Typical power consumption <0.1 µW
TTL/CMOS compatible inputs
Package upgrades to 74HC4051/74HC4052 and
MAX4051/MAX4052/MAX4581/MAX4582
demultiplexers and have an input range that extends to the
supplies. All channels exhibit break-before-make switching
action, preventing momentary shorting when switching
channels. All digital inputs have 0.8 V to 2.4 V logic thresholds,
ensuring TTL/CMOS logic compatibility when using single
+5 V or dual ±5 V supplies.
The ADG658 and ADG659 are available in 16-lead TSSOP/
QSOP packages and 16-lead 4 mm × 4 mm LFCSP packages.
PRODUCT HIGHLIGHTS
1. Single- and dual-supply operation.
The ADG658 and ADG659 offer high performance and are
fully specified and guaranteed with ±5 V, +5 V, and +3 V
supply rails.
2. Automotive temperature range −40°C to +125°C.
3. Low power consumption, typically <0.1 µW.
4. 16-lead 4 mm × 4 mm LFCSP packages, 16-lead TSSOP
package and 16-lead QSOP package.
APPLICATIONS
Automotive applications
Automatic test equipment
Data acquisition systems
Battery-powered systems
Communication systems
Audio and video signal routing
Relay replacement
Sample-and-hold systems
Industrial control systems
FUNCTIONAL BLOCK DIAGRAM
ADG658
S1
S1A
DA
S4A
D
S1B
DB
S8
1 OF 8
DECODER
S4B
1 OF 4
DECODER
ADG659
GENERAL DESCRIPTION
The ADG658 and ADG659 are low voltage, CMOS analog
multiplexers comprised of eight single channels and four
differential channels, respectively. The ADG658 switches one of
eight inputs (S1–S8) to a common output, D, as determined by
the 3-bit binary address lines A0, A1, and A2. The ADG659
switches one of four differential inputs to a common differential
output, as determined by the 2-bit binary address lines A0 and
A1. An EN input on both devices is used to enable or disable
the device. When disabled, all channels are switched off.
These parts are designed on an enhanced process that provides
lower power dissipation yet gives high switching speeds. These
parts can operate equally well as either multiplexers or
A0
A1
A2
EN
A0
A1
EN
SWITCHES SHOWN FOR A LOGIC 1 INPUT
Figure 1.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.326.8703
© 2004 Analog Devices, Inc. All rights reserved.
03273-0-001
ADG658/ADG659
TABLE OF CONTENTS
Specifications: Dual Supply ............................................................. 3
Specifications: Single Supply 5V..................................................... 5
Specifications: Single Supply 2.7 to 3.6 V...................................... 7
Absolute Maximum Ratings............................................................ 9
ESD Caution.................................................................................. 9
Pin Configuration and Function Descriptions........................... 11
Typical Performance Characteristics ........................................... 13
Test Circuits ................................................................................ 16
Outline Dimensions ....................................................................... 19
Ordering Guide .......................................................................... 20
REVISION HISTORY
7/04—Data Sheet Changed from Rev. 0 to Rev. A
Updated Format.............................................................. Universal
Added QSOP Package Outline .................................................. 20
Changes to Ordering Guide ....................................................... 20
3/03—Rev. 0: Initial Version
Rev. A | Page 2 of 20
ADG658/ADG659
SPECIFICATIONS: DUAL SUPPLY
V
DD
= +5 V ± 10%, V
SS
= −5 V ± 10%, GND = 0 V, unless otherwise noted.
1
Table 1.
B Version
−40°C
to +85°C
Y Version
−40°C
to+125°C
V
SS
to V
DD
45
75
1.3
3
10
16
±0.005
±0.2
±0.005
±0.2
±0.1
±0.005
±0.2
±0.1
90
3.2
17
100
3.5
18
Parameter
ANALOG SWITCH
Analog Signal Range
On Resistance (R
ON
)
On Resistance Match between
Channels (∆R
ON
)
On Resistance Flatness (R
FLAT(ON)
)
LEAKAGE CURRENTS
Source OFF Leakage I
S
(OFF)
Drain OFF Leakage I
D
(OFF)
ADG658
ADG659
Channel ON Leakage I
D
, I
S
(ON)
ADG658
ADG659
DIGITAL INPUTS
Input High Voltage, V
INH
Input Low Voltage, V
INL
Input Current
I
INL
or I
INH
C
IN
, Digital Input Capacitance
DYNAMIC CHARACTERISTICS
2
t
TRANS
t
ON
(EN)
t
OFF
(EN)
Break-Before-Make Time Delay, t
BBM
Charge Injection
Off Isolation
Total Harmonic Distortion, THD + N
Channel-to-Channel Crosstalk
(ADG659)
−3 dB Bandwidth
ADG658
ADG659
C
S
(OFF)
C
D
(OFF)
ADG658
ADG659
+25°C
Unit
V
Ω typ
Ω max
Ω typ
Ω max
Ω typ
Ω max
nA typ
nA max
nA typ
nA max
nA max
nA typ
nA max
nA max
V min
V max
µA typ
µA max
pF typ
ns typ
ns max
ns typ
ns max
ns typ
ns max
ns typ
ns min
pC typ
pC max
dB typ
% typ
dB typ
MHz typ
MHz typ
pF typ
pF typ
pF typ
Test Conditions/Comments
V
DD
= +4.5 V, V
SS
= −4.5 V
V
S
= ±4.5 V, I
S
= 1 mA;
Test Circuit 1
V
S
= 3.5 V, I
S
= 1 mA
V
DD
= +5 V, V
SS
= −5 V;
V
S
= ±3 V, I
S
= 1 mA
V
DD
= +5.5 V, V
SS
= −5.5 V
V
D
= ±4.5 V, V
S
=
m
4.5 V;
Test Circuit 2
V
D
= ±4.5 V, V
S
=
m
4.5 V;
Test Circuit 3
V
D
= V
S
= ±4.5 V; Test Circuit 4
±5
±5
±2.5
±5
±2.5
2.4
0.8
0.005
±1
2
80
115
80
115
30
45
50
2
4
−90
0.025
−90
210
400
4
23
12
V
IN
= V
INL
or V
INH
140
140
50
165
165
55
10
R
L
= 300 Ω, C
L
= 35 pF
V
S
= 3 V; Test Circuit 5
R
L
= 300 Ω, C
L
= 35 pF
V
S
= 3 V; Test Circuit 7
R
L
= 300 Ω, C
L
= 35 pF
V
S
= 3 V; Test Circuit 7
R
L
= 300 Ω, C
L
= 35 pF
V
S1
= V
S2
= 3 V; Test Circuit 6
V
S
= 0 V, R
S
= 0 Ω,
C
L
= 1 nF; Test Circuit 8
R
L
= 50 Ω, C
L
= 5 pF, f = 1 MHz; Test Circuit 9
R
L
= 600 Ω, 2 V p-p, f = 20 Hz to 20 kHz
R
L
= 50 Ω, C
L
= 5 pF, f = 1 MHz; Test Circuit 11
R
L
= 50 Ω, C
L
= 5 pF;
Test Circuit 10
f = 1 MHz
f = 1 MHz
f = 1 MHz
Rev. A | Page 3 of 20
ADG658/ADG659
B Version
−40°C
to +85°C
Y Version
−40°C
to+125°C
Parameter
C
D
, C
S
(ON)
ADG658
ADG659
POWER REQUIREMENTS
I
DD
I
SS
+25°C
28
16
0.01
Unit
pF typ
pF typ
µA typ
µA max
µA typ
µA max
Test Conditions/Comments
f = 1 MHz
f = 1 MHz
V
DD
= +5.5 V, V
SS
= −5.5 V
Digital Inputs = 0 V or 5.5 V
Digital Inputs = 0 V or 5.5 V
1
0.01
1
1
2
Temperature range is as follows: B Version: −40°C to +85°C. Y Version: −40°C to +125°C.
Guaranteed by design; not subject to production test.
Rev. A | Page 4 of 20
ADG658/ADG659
SPECIFICATIONS: SINGLE SUPPLY 5V
V
DD
= 5 V ± 10%, V
SS
= 0 V, GND = 0 V, unless otherwise noted.
1
Table 2.
B Version
−40°C
to +85°C
Y Version
−40°C
to +125°C
0 to V
DD
85
150
4.5
8
13
160
9
14
200
10
16
Parameter
ANALOG SWITCH
Analog Signal Range
On Resistance (R
ON
)
On Resistance Match between
Channels (∆R
ON
)
On Resistance Flatness (R
FLAT(ON)
)
LEAKAGE CURRENTS
Source OFF Leakage I
S
(OFF)
Drain OFF Leakage I
D
(OFF)
ADG658
ADG659
Channel ON Leakage I
D
, I
S
(ON)
ADG658
ADG659
DIGITAL INPUTS
Input High Voltage, V
INH
Input Low Voltage, V
INL
Input Current
I
INL
or I
INH
C
IN
, Digital Input Capacitance
DYNAMIC CHARACTERISTICS
2
t
TRANS
t
ON
(EN)
t
OFF
(EN)
Break-Before-Make Time Delay, t
BBM
Charge Injection
Off Isolation
Channel-to-Channel Crosstalk
(ADG659)
−3 dB Bandwidth
ADG658
ADG659
C
S
(OFF)
C
D
(OFF)
ADG658
ADG659
+25°C
Unit
V
Ω typ
Ω max
Ω typ
Ω max
Ω typ
Test Conditions/Comments
V
DD
= 4.5 V, V
SS
= 0 V
V
S
= 0 V to 4.5 V, I
S
= 1 mA;
Test Circuit 1
V
S
= 3.5 V, I
S
= 1 mA
V
DD
= 5 V, V
SS
= 0 V
V
S
= 1.5 V to 4 V, I
S
= 1 mA
V
DD
= 5.5 V
V
S
= 1 V/4.5 V, V
D
= 4.5 V/1 V;
Test Circuit 2
V
S
= 1 V/4.5 V, V
D
= 4.5 V/1 V;
Test Circuit 3
V
S
= V
D
= 1 V or 4.5 V, Test Circuit 4
±0.005
±0.2
±0.005
±0.2
±0.1
±0.005
±0.2
±0.1
±5
±5
±2.5
±5
±2.5
2.4
0.8
nA typ
nA max
nA typ
nA max
nA max
nA typ
nA max
nA max
V min
V max
µA typ
µA max
pF typ
ns typ
ns max
ns typ
ns max
ns typ
ns max
ns typ
ns min
pC typ
pC max
dB typ
dB typ
0.005
±1
2
120
200
120
190
35
50
100
0.5
1
−90
−90
V
IN
= V
INL
or V
INH
270
245
60
300
280
70
10
R
L
= 300 Ω, C
L
= 35 pF
V
S
= 3 V; Test Circuit 5
R
L
= 300 Ω, C
L
= 35 pF
V
S
= 3 V; Test Circuit 7
R
L
= 300 Ω, C
L
= 35 pF
V
S
= 3 V; Test Circuit 7
R
L
= 300 Ω, C
L
= 35 pF
V
S1
= V
S2
= 3 V; Test Circuit 6
V
S
= 2.5 V, R
S
= 0 Ω, C
L
= 1 nF;
Test Circuit 8
R
L
= 50 Ω, C
L
= 5 pF, f = 1 MHz; Test Circuit 9
R
L
= 50 Ω, C
L
= 5 pF; f = 1 MHz;
Test Circuit 11
R
L
= 50 Ω, C
L
= 5 pF;
Test Circuit 10
f = 1 MHz
f = 1 MHz
f = 1 MHz
180
330
5
29
15
MHz typ
MHz typ
pF typ
pF typ
pF typ
Rev. A | Page 5 of 20
