Typical values are specified at 25°C and IMOD = 10 mA with crosspoint adjust disabled, unless otherwise noted.
Table 1.
Parameter
BIAS CURRENT (IBIAS)
Bias Current Range
Bias Current While ALS Asserted
Compliance Voltage
1
MODULATION CURRENT (IMODP, IMODN)
Modulation Current Range
Modulation Current While ALS Asserted
Crosspoint Adjust (CPA) Range
2
Rise Time (20% to 80%)
2, 3, 4
Fall Time (20% to 80%)
2, 3, 4
Random Jitter
2, 3, 4
Deterministic Jitter
2, 4, 5
Deterministic Jitter
2, 4, 6
Differential |S22|
Compliance Voltage
1
DATA INPUTS (DATAP, DATAN)
Input Data Rate
Differential Input Swing
Differential |S11|
Input Termination Resistance
BIAS CONTROL INPUT (BSET)
BSET Voltage to IBIAS Gain
BSET Input Resistance
MODULATION CONTROL INPUT (MSET)
MSET Voltage to IMOD Gain
MSET Input Resistance
BIAS MONITOR (IBMON)
IBMON to IBIAS Ratio
Accuracy of IBIAS to IBMON Ratio
VCC − 0.7
Min
2
0.55
0.55
2.2
2.2
35
26
26.4
26
26.5
<0.5
<0.5
5.4
5.8
5.4
5.8
−5
−13.6
Typ
Max
25
50
VCC – 1.3
VCC – 0.8
23
19
250
65
32.5
34.7
32.5
33.7
Unit
mA
μA
V
V
mA diff
mA diff
μA diff
%
ps
ps
ps
ps
ps rms
ps rms
ps p-p
ps p-p
ps p-p
ps p-p
dB
dB
V
Gbps
V p-p diff
dB
Ω
mA/V
Ω
mA/V
Ω
μA/mA
%
%
%
%
%
V
V
μA
μA
Test Conditions/Comments
ALS = high
IBIAS = 25 mA
IBIAS = 2 mA
R
LOAD
= 35 Ω to 100 Ω differential
R
LOAD
= 140 Ω differential
ALS = high
CPA disabled
CPA 35% to 65%
CPA disabled
CPA 35% to 65%
CPA disabled
CPA 35% to 65%
10.7 Gbps, CPA disabled
10.7 Gbps, CPA 35% to 65%
11.3 Gbps, CPA disabled
11.3 Gbps, CPA 35% to 65%
5 GHz < f < 10 GHz, Z
0
= 100 Ω differential
f < 5 GHz, Z
0
= 100 Ω differential
8.2
8.2
8.2
8.2
VCC + 0.7
11.3
1.6
−15
100
20
1000
19
1000
50
115
24
1200
23
1200
0.4
85
15
800
14
800
NRZ
Differential ac-coupled
f < 10 GHz, Z
0
= 100 Ω differential
Differential
−5.0
−4.3
−3.5
−3.0
−2.5
2.4
−20
0
+5.0
+4.3
+3.5
+3.0
+2.5
IBIAS = 2 mA, R
IBMON
= 750 Ω
IBIAS = 4 mA, R
IBMON
= 750 Ω
IBIAS = 8 mA, R
IBMON
= 750 Ω
IBIAS = 14 mA, R
IBMON
= 750 Ω
IBIAS = 25 mA, R
IBMON
= 750 Ω
AUTOMATIC LASER SHUTDOWN (ALS)
V
IH
V
IL
I
IL
I
IH
0.8
+20
200
Rev. A | Page 3 of 20
ADN2530
Parameter
ALS Assert Time
ALS Negate Time
POWER SUPPLY
V
CC
I
CC 7
I
SUPPLY 8
1
2
Min
Typ
Max
2
10
Unit
μs
μs
Test Conditions/Comments
Rising edge of ALS to fall of IBIAS and IMOD
below 10% of nominal; see Figure 2
Falling edge of ALS to rise of IBIAS and IMOD
above 90% of nominal; see Figure 2
3.07
3.3
27
65
3.53
32
76
V
mA
mA
V
BSET
= V
MSET
= 0 V
V
BSET
= V
MSET
= 0 V
The voltage between the pin with the specified compliance voltage and GND.
Specified for T
A
= −40°C to +85°C due to test equipment limitation. See the Typical Performance Characteristics section for data on performance for T
A
= −40°C to +100°C.
3
The pattern used is composed of a repetitive sequence of eight 1s followed by eight 0s at 10.7 Gbps.
4
Measured using the high speed characterization circuit shown in Figure 3.
5
The pattern used is K28.5 (00111110101100000101) at 10.7 Gbps rate.
6
The pattern used is K28.5 (00111110101100000101) at 11.3 Gbps rate.
7
Only includes current in the ADN2530 VCC pins.
8
Includes current in ADN2530 VCC pins and dc current in IMODP and IMODN pull-up inductors. See the Power Consumption section for total supply current calculation.
PACKAGE THERMAL SPECIFICATIONS
Table 2.
Parameter
θ
J-TOP
θ
J-PAD
IC Junction Temperature
Min
65
2.6
Typ
72.2
5.8
Max
79.4
10.7
125
ALS
Unit
°C/W
°C/W
°C
Conditions/Comments
Thermal resistance from junction to top of package.
Thermal resistance from junction to bottom of exposed pad.
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