Continuous Rate 12.3 Mb/s to 2.7 Gb/s Clock and
Data Recovery IC with Integrated Limiting Amp
Data Sheet
FEATURES
Serial data input: 12.3 Mb/s to 2.7 Gb/s
Exceeds SONET requirements for jitter transfer/
generation/tolerance
Quantizer sensitivity: 6 mV typical
Adjustable slice level: ±100 mV
Patented clock recovery architecture
Loss of signal (LOS) detect range: 3 mV to 15 mV
Independent slice level adjust and LOS detector
No reference clock required
Loss of lock indicator
I
2
C interface to access optional features
Single-supply operation: 3.3 V
Low power: 750 mW typical
5 mm × 5 mm 32-lead LFCSP
ADN2812
GENERAL DESCRIPTION
The ADN2812 provides the receiver functions of quantization,
signal level detect, and clock and data recovery for continuous
data rates from 12.3 Mb/s to 2.7 Gb/s. The ADN2812 auto-
matically locks to all data rates without the need for an external
reference clock or programming. All SONET jitter requirements
are met, including jitter transfer, jitter generation, and jitter
tolerance. All specifications are quoted for −40°C to +85°C
ambient temperature, unless otherwise noted.
This device, together with a PIN diode and a TIA preamplifier,
can implement a highly integrated, low cost, low power fiber
optic receiver.
The receiver front end, loss of signal (LOS) detector circuit
indicates when the input signal level has fallen below a user-
adjustable threshold. The LOS detect circuit has hysteresis to
prevent chatter at the output.
The ADN2812 is available in a compact 5 mm × 5 mm 32-lead
lead frame chip scale package (LFCSP).
APPLICATIONS
SONET OC-1/OC-3/OC-12/OC-48 and all associated FEC rates
Fibre Channel, 2× Fibre Channel, GbE, HDTV
WDM transponders
Regenerators/repeaters
Test equipment
Broadband cross-connects and routers
FUNCTIONAL BLOCK DIAGRAM
REFCLKP/N
(OPTIONAL)
LOL
CF1
CF2
VCC
VEE
2
SLICEP/N
PIN
NIN
QUANTIZER
PHASE
SHIFTER
FREQUENCY
DETECT
LOOP
FILTER
PHASE
DETECT
LOOP
FILTER
VCO
VREF
LOS
DETECT
DATA
RE-TIMING
2
2
THRADJ
LOS
DATAOUTP/N
CLKOUTP/N
04228-001
Figure 1.
Rev. E
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2004–2012 Analog Devices, Inc. All rights reserved.
ADN2812
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Jitter Specifications ....................................................................... 4
Output and Timing Specifications ............................................. 5
Absolute Maximum Ratings ............................................................ 6
Thermal Characteristics .............................................................. 6
ESD Caution .................................................................................. 6
Timing Characteristics ..................................................................... 7
Pin Configuration and Function Descriptions ............................. 8
Typical Performance Characteristics ............................................. 9
I
2
C Interface Timing and Internal Register Description ........... 10
Terminology .................................................................................... 12
Input Sensitivity and Input Overdrive ..................................... 12
Single-Ended vs. Differential .................................................... 12
LOS Response Time ................................................................... 12
Jitter Specifications ......................................................................... 13
Data Sheet
Jitter Generation ......................................................................... 13
Jitter Transfer .............................................................................. 13
Jitter Tolerance ............................................................................ 13
Theory of Operation ...................................................................... 14
Functional Description .................................................................. 16
Frequency Acquisition ............................................................... 16
Limiting Amplifier ..................................................................... 16
Slice Adjust .................................................................................. 16
LOS Detector .............................................................................. 16
Lock Detector Operation .......................................................... 16
Harmonic Detector .................................................................... 17
Squelch Mode ............................................................................. 17
I
2
C Interface ................................................................................ 18
Reference Clock (Optional) ...................................................... 18
Applications Information .............................................................. 21
PCB Design Guidelines ............................................................. 21
DC-Coupled Application .......................................................... 23
Coarse Data Rate Readback Look-Up Table ............................... 24
Outline Dimensions ....................................................................... 26
Ordering Guide .......................................................................... 26
REVISION HISTORY
3/12—Rev. D to Rev. E
Updated Outline Dimensions ....................................................... 26
Changes to Ordering Guide .......................................................... 26
5/10—Rev. C to Rev. D
Changes to Figure 4, Table 5 ........................................................... 8
Changes to Figure 24 ...................................................................... 21
2/09—Rev. B to Rev. C
Updated Outline Dimensions ....................................................... 26
Changes to Ordering Guide .......................................................... 26
6/07—Rev. A to Rev. B
Changes to Table 1 ............................................................................ 3
Changes to Table 6 .......................................................................... 11
Changes to LTR Mode Description ............................................. 19
Changes to Ordering Guide .......................................................... 26
11/04—Rev. 0 to Rev. A
Change to Specification ....................................................................3
Updated Outline Dimensions ....................................................... 26
Changes to Using the Reference Clock to Lock onto Data
Section .............................................................................................. 19
3/04—Revision 0: Initial Version
Rev. E | Page 2 of 28
Data Sheet
SPECIFICATIONS
ADN2812
T
A
= T
MIN
to T
MAX
, VCC = V
MIN
to V
MAX
, VEE = 0 V, C
F
= 0.47 µF, SLICEP = SLICEN = VEE, input data pattern: PRBS 2
23
− 1,
unless otherwise noted.
Table 1.
Parameter
QUANTIZER—DC CHARACTERISTICS
Input Voltage Range
Peak-to-Peak Differential Input
Input Common-Mode Level
Differential Input Sensitivity
Input Overdrive
Input Offset
Input RMS Noise
QUANTIZER—AC CHARACTERISTICS
Data Rate
S11
Input Resistance
Input Capacitance
QUANTIZER—SLICE ADJUSTMENT
Gain
Differential Control Voltage Input
Control Voltage Range
Slice Threshold Offset
LOSS OF SIGNAL DETECT (LOS)
Loss of Signal Detect Range
Hysteresis (Electrical)
Conditions
@ PIN or NIN, dc-coupled
PIN – NIN
DC-coupled (see Figure 28, Figure 29,
and Figure 30)
2
23
− 1 PRBS, ac-coupled,
1
BER = 1 × 10
–10
(see Figure 12)
BER = 1 x 10
–10
12.3
@ 2.5 GHz
Differential
−15
100
0.65
0.08
−0.95
VEE
0.1
0.125
+0.95
0.95
Min
1.8
2.3
10
5
2.5
6
3
500
290
2700
Typ
Max
2.8
2.0
2.8
Unit
V
V
V
mV p-p
mV p-p
µV
µV rms
Mb/s
dB
Ω
pF
V/V
V
V
mV
mV
mV
dB
dB
dB
dB
ns
ns
ppm
ppm
ms
µs
µs
ms
ms
ms
ms
ms
ms
SLICEP – SLICEN = ±0.5 V
SLICEP – SLICEN
DC level @ SLICEP or SLICEN
1
R
Thresh
= 0 Ω (see Figure 5)
R
Thresh
= 100 kΩ
OC-48
R
Thresh
= 0 Ω
R
Thresh
= 100 kΩ
OC-1
R
Thresh
= 0 Ω
R
Thresh
= 10 kΩ
DC-coupled
2
DC-coupled
2
With respect to nominal
With respect to nominal
12.3 Mb/s
OC-12
OC-48
OC-48
OC-12
OC-3
OC-1
12.3 Mb/s
11
1.5
5.6
3.7
5.6
2.0
13
3
6
6
6
4
500
450
1000
250
4
1.0
1.0
1.3
2.0
3.4
9.8
40.0
10.0
17
4.0
7.2
8.4
7.2
6.7
LOS Assert Time
LOS Deassert Time
LOSS OF LOCK DETECT (LOL)
VCO Frequency Error for LOL Assert
VCO Frequency Error for LOL Deassert
LOL Response Time
ACQUISITION TIME
Lock to Data Mode
Optional Lock to REFCLK Mode
Rev. E | Page 3 of 28
ADN2812
Parameter
DATA RATE READBACK ACCURACY
Coarse Readback
Fine Readback
Conditions
See Table 14
In addition to REFCLK accuracy
Data rate ≤ 20 Mb/s
Data rate > 20 Mb/s
3.0
–40
Min
Typ
10
200
100
3.6
259
+85
Data Sheet
Max
Unit
%
ppm
ppm
V
mA
°C
POWER SUPPLY VOLTAGE
POWER SUPPLY CURRENT
OPERATING TEMPERATURE RANGE
1
2
3.3
235
PIN and NIN should be differentially driven and ac-coupled for optimum sensitivity.
When ac-coupled, the LOS assert and deassert time is dominated by the RC time constant of the ac coupling capacitor and the 50 Ω input termination of the
ADN2812 input stage.
JITTER SPECIFICATIONS
T
A
= T
MIN
to T
MAX
, VCC = V
MIN
to V
MAX
, VEE = 0 V, C
F
= 0.47 µF, SLICEP = SLICEN = VEE, input data pattern: PRBS 2
23
− 1,
unless otherwise noted.
Table 2.
Parameter
PHASE-LOCKED LOOP CHARACTERISTICS
Jitter Transfer BW
Conditions
OC-48
OC-12
OC-3
OC-48
OC-12
OC-3
OC-48, 12 kHz to 20 MHz
OC-12, 12 kHz to 5 MHz
OC-3, 12 kHz to 1.3 MHz
Jitter Tolerance
OC-48, 2
23
− 1 PRBS
600 Hz
6 kHz
100 kHz
1 MHz
20 MHz
OC-12, 2
23
− 1 PRBS
30 Hz
1
300 Hz
1
25 kHz
250 kHz
1
OC-3, 2
23
− 1 PRBS
30 Hz
1
300 Hz
1
6500 Hz
65 kHz
Min
Typ
490
71
23
0
0
0
0.001
0.02
0.001
0.01
0.001
0.01
70
19
3.8
0.75
0.4
100
44
2.5
1.0
50
24
3.5
1.0
92
45
5
1
0.6
Max
670
108
35
0.03
0.03
0.03
0.002
0.037
0.002
0.019
0.002
0.011
Unit
kHz
kHz
kHz
dB
dB
dB
UI rms
UI p-p
UI rms
UI p-p
UI rms
UI p-p
UI p-p
UI p-p
UI p-p
UI p-p
UI p-p
UI p-p
UI p-p
UI p-p
UI p-p
UI p-p
UI p-p
UI p-p
UI p-p
Jitter Peaking
Jitter Generation
1
Jitter tolerance of the ADN2812 at these jitter frequencies is better than what the test equipment is able to measure.
Rev. E | Page 4 of 28
Data Sheet
OUTPUT AND TIMING SPECIFICATIONS
Table 3.
Parameter
CML OUPUT CHARACTERISTICS
(CLKOUTP/CLKOUTN, DATAOUTP/DATAOUTN)
Single-Ended Output Swing
Differential Output Swing
Output High Voltage
Output Low Voltage
CML Outputs Timing
Rise Time
Fall Time
Setup Time
Hold Time
I
2
C® INTERFACE DC CHARACTERISTICS
Input High Voltage
Input Low Voltage
Input Current
Output Low Voltage
2
I C INTERFACE TIMING
SCK Clock Frequency
SCK Pulse Width High
SCK Pulse Width Low
Start Condition Hold Time
Start Condition Setup Time
Data Setup Time
Data Hold Time
SCK/SDA Rise/Fall Time
Stop Condition Setup Time
Bus Free Time Between a Stop and a Start
REFCLK CHARACTERISTICS
Input Voltage Range
Conditions
Min
Typ
Max
ADN2812
Unit
V
SE
(see Figure 3)
V
DIFF
(see Figure 3)
V
OH
V
OL
20% to 80%
80% to 20%
t
S
(see Figure 2), OC-48
t
H
(see Figure 2), OC-48
LVCMOS
V
IH
V
IL
V
IN
= 0.1 VCC or V
IN
= 0.9 VCC
V
OL
, I
OL
= 3.0 mA
See Figure 11
t
HIGH
t
LOW
t
HD;STA
t
SU;STA
t
SU;DAT
t
HD;DAT
t
R
/t
F
t
SU;STO
t
BUF
Optional lock to REFCLK mode
@ REFCLKP or REFCLKN
V
IL
V
IH
300
600
VCC − 0.6
350
700
VCC − 0.35
95
95
200
200
600
1200
VCC
VCC − 0.3
112
123
250
250
mV
mV
V
V
ps
ps
ps
ps
V
V
µA
V
kHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
150
150
0.7 VCC
−10.0
0.3 VCC
+10.0
0.4
400
600
1300
600
600
100
300
20 + 0.1 Cb
1
600
1300
300
Minimum Differential Input Drive
Reference Frequency
Required Accuracy
LVTTL DC INPUT CHARACTERISTICS
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
LVTTL DC OUTPUT CHARACTERISTICS
Output High Voltage
Output Low Voltage
1
0
VCC
100
12.3
100
200
V
V
mV p-p
MHz
ppm
V
V
µA
µA
V
V
V
IH
V
IL
I
IH
, V
IN
= 2.4 V
I
IL
, V
IN
= 0.4 V
V
OH
, I
OH
= −2.0 mA
V
OL
, I
OL
= +2.0 mA
2.0
0.8
5
−5
2.4
0.4
Cb = total capacitance of one bus line in pF. If mixed with HS mode devices, faster fall-times are allowed (see Table 6).
Rev. E | Page 5 of 28
