Changes to Ordering Guide .......................................................... 23
8/10—Rev. 0 to Rev. A
Changes to Figure 8 ...........................................................................7
Changes to Figure 15 Caption and Figure 16 Caption .................8
Changes to Figure 17 Caption and Figure 18 Caption .................9
Changes to Ordering Guide .......................................................... 21
3/10—Revision 0: Initial Version
Rev. D | Page 2 of 24
ADP151
SPECIFICATIONS
V
IN
= (V
OUT
+ 0.4 V) or 2.2 V, whichever is greater; EN = V
IN
, I
OUT
= 10 mA, C
IN
= C
OUT
= 1 µF, T
A
= 25°C, unless otherwise noted.
Table 1.
Parameter
INPUT VOLTAGE RANGE
OPERATING SUPPLY CURRENT
Symbol
V
IN
I
GND
Conditions
T
J
= −40°C to +125°C
I
OUT
= 0 µA
I
OUT
= 0 µA, T
J
= −40°C to +125°C
I
OUT
= 100 µA
I
OUT
= 100 µA, T
J
= −40°C to +125°C
I
OUT
= 10 mA
I
OUT
= 10 mA, T
J
= −40°C to +125°C
I
OUT
= 200 mA
I
OUT
= 200 mA, T
J
= −40°C to +125°C
EN = GND
EN = GND, T
J
= −40°C to +125°C
I
OUT
= 10 mA
T
J
= −40°C to +125°C
V
OUT
< 1.8 V
100 µA < I
OUT
< 200 mA, V
IN
= (V
OUT
+ 0.4 V) to 5.5 V
V
OUT
≥1.8 V
100 µA < I
OUT
< 200 mA, V
IN
= (V
OUT
+ 0.4 V) to 5.5 V
T
J
= −40°C to +125°C
V
OUT
< 1.8 V
100 µA < I
OUT
< 200 mA, V
IN
= (V
OUT
+ 0.4 V) to 5.5 V
V
OUT
≥1.8 V
100 µA < I
OUT
< 200 mA, V
IN
= (V
OUT
+ 0.4 V) to 5.5 V
V
IN
= (V
OUT
+ 0.4 V) to 5.5 V, T
J
= −40°C to +125°C
V
OUT
< 1.8 V
I
OUT
= 100 µA to 200 mA
I
OUT
= 100 µA to 200 mA, T
J
= −40°C to +125°C
V
OUT
≥ 1.8 V
I
OUT
= 100 µA to 200 mA
I
OUT
= 100 µA to 200 mA, T
J
= −40°C to +125°C
V
OUT
< 1.8 V
I
OUT
= 100 µA to 200 mA
I
OUT
= 100 µA to 200 mA, T
J
= −40°C to +125°C
V
OUT
≥1.8 V
I
OUT
= 100 µA to 200 mA
I
OUT
= 100 µA to 200 mA, T
J
= −40°C to +125°C
I
OUT
= 10 mA
I
OUT
= 10 mA, T
J
= −40°C to +125°C
I
OUT
= 200 mA
I
OUT
= 200 mA, T
J
= −40°C to +125°C
I
OUT
= 200 mA
I
OUT
= 200 mA, T
J
= −40°C to +125°C
Min
2.2
Typ
10
20
20
40
60
90
265
350
0.2
1.0
−1
+1
Max
5.5
Unit
V
µA
µA
µA
µA
µA
µA
μA
μA
µA
µA
%
SHUTDOWN CURRENT
OUTPUT VOLTAGE ACCURACY
TSOT/LFCSP
I
GND-SD
V
OUT
V
OUT
−3
−2.5
+2
+1.5
%
%
WLCSP
V
OUT
−2.5
−2
−0.05
0.006
+2
+1.5
+0.05
%
%
%/V
%/mA
%/mA
%/mA
%/mA
%/mA
%/mA
%/mA
%/mA
%/mA
%/mA
mV
mV
mV
mV
mV
mV
REGULATION
Line Regulation
Load Regulation (TSOT/LFCSP)
1
∆V
OUT
/∆V
IN
∆V
OUT
/∆I
OUT
0.012
0.003
0.008
0.004
0.009
0.002
0.006
10
30
150
230
135
200
Load Regulation (WLCSP)
1
∆V
OUT
/∆I
OUT
DROPOUT VOLTAGE
TSOT/LFCSP
WLCSP
2
V
DROPOUT
Rev. D | Page 3 of 24
ADP151
Parameter
START-UP TIME
3
CURRENT-LIMIT THRESHOLD
4
UNDERVOLTAGE LOCKOUT
Input Voltage Rising
Input Voltage Falling
Hysteresis
THERMAL SHUTDOWN
Thermal Shutdown Threshold
Thermal Shutdown Hysteresis
EN INPUT
EN Input Logic High
EN Input Logic Low
EN Input Pull-Down Resistance
OUTPUT NOISE
Symbol
t
START-UP
I
LIMIT
UVLO
RISE
UVLO
FALL
UVLO
HYS
TS
SD
TS
SD-HYS
V
IH
V
IL
R
EN
OUT
NOISE
T
J
rising
Conditions
V
OUT
= 3.3 V
T
J
= 0°C to +125°C
T
J
= −40°C to +125°C
Min
220
Typ
180
300
Max
400
1.96
1.28
120
150
15
1.2
0.4
2.6
9
9
9
70
55
70
55
70
55
Unit
µs
mA
V
V
mV
°C
°C
V
V
MΩ
µV rms
µV rms
µV rms
dB
dB
dB
dB
dB
dB
2.2 V ≤ V
IN
≤ 5.5 V
2.2 V ≤ V
IN
≤ 5.5 V
V
IN
= V
EN
= 5.5 V
10 Hz to 100 kHz, V
IN
= 5 V, V
OUT
= 3.3 V
10 Hz to 100 kHz, V
IN
= 5 V, V
OUT
= 2.5 V
10 Hz to 100 kHz, V
IN
= 5 V, V
OUT
= 1.1 V
10 kHz, V
IN
= 3.8 V, V
OUT
= 3.3 V, I
OUT
= 10 mA
100 kHz, V
IN
= 3.8 V, V
OUT
= 3.3 V, I
OUT
= 10 mA
10 kHz, V
IN
= 4.3 V, V
OUT
= 3.3 V, I
OUT
= 10 mA
100 kHz, V
IN
= 4.3 V, V
OUT
= 3.3 V, I
OUT
= 10 mA
10 kHz, V
IN
= 2.2 V, V
OUT
= 1.1 V, I
OUT
= 10 mA
100 kHz, V
IN
= 2.2 V, V
OUT
= 1.1 V, I
OUT
= 10 mA
POWER SUPPLY REJECTION RATIO
V
IN
= V
OUT
+ 0.5 V
V
IN
= V
OUT
+ 1 V
PSRR
1
2
Based on an end-point calculation using 0.1 mA and 200 mA loads. See Figure 8 for typical load regulation performance for loads less than 1 mA.
Dropout voltage is defined as the input-to-output voltage differential when the input voltage is set to the nominal output voltage. This applies only for output
voltages above 2.2 V.
3
Start-up time is defined as the time between the rising edge of EN and V
OUT
being at 90% of its nominal value.
4
Current-limit threshold is defined as the current at which the output voltage drops to 90% of the specified typical value. For example, the current limit for a 3.0 V
output voltage is defined as the current that causes the output voltage to drop to 90% of 3.0 V (that is, 2.7 V).
INPUT AND OUTPUT CAPACITOR, RECOMMENDED SPECIFICATIONS
Table 2.
Parameter
Minimum Input and Output
Capacitance
1
Capacitor ESR
1
Symbol
C
MIN
R
ESR
Conditions
T
A
= −40°C to +125°C
T
A
= −40°C to +125°C
Min
0.7
0.001
Typ
Max
Unit
µF
Ω
0.2
The minimum input and output capacitance should be greater than 0.7 μF over the full range of operating conditions. The full range of operating conditions in the
application must be considered during device selection to ensure that the minimum capacitance specification is met. X7R and X5R type capacitors are recommended;
Y5V and Z5U capacitors are not recommended for use with any LDO.
Rev. D | Page 4 of 24
ADP151
ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter
VIN to GND
VOUT to GND
EN to GND
Storage Temperature Range
Operating Junction Temperature Range
Operating Ambient Temperature Range
Soldering Conditions
Rating
−0.3 V to +6.5 V
−0.3 V to VIN
−0.3 V to +6.5V
−65°C to +150°C
−40°C to +125°C
−40°C to +125°C
JEDEC J-STD-020
on PCB material, layout, and environmental conditions. The
specified values of θ
JA
are based on a 4-layer, 4 in. × 3 in. circuit
board. See JESD51-7 and JESD51-9 for detailed information
on the board construction. For additional information, see the
AN-617 Application Note,
MicroCSP™ Wafer Level Chip Scale
Package,
available at
www.analog.com.
Ψ
JB
is the junction-to-board thermal characterization parameter
with units of °C/W. Ψ
JB
of the package is based on modeling and
calculation using a 4-layer board. The JESD51-12,
Guidelines for
Reporting and Using Electronic Package Thermal Information,
states
that thermal characterization parameters are not the same as
thermal resistances. Ψ
JB
measures the component power flowing
through multiple thermal paths rather than a single path as in
thermal resistance, θ
JB
. Therefore, Ψ
JB
thermal paths include
convection from the top of the package as well as radiation from
the package, factors that make Ψ
JB
more useful in real-world
applications. Maximum junction temperature (T
J
) is calculated
from the board temperature (T
B
) and power dissipation (P
D
)
using the formula
T
J
=
T
B
+ (P
D
×
Ψ
JB
)
See JESD51-8 and JESD51-12 for more detailed information
about Ψ
JB
.
Stresses above those listed under absolute maximum ratings
may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or
any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL DATA
Absolute maximum ratings apply individually only, not in
combination. The ADP151 can be damaged when the junction
temperature limits are exceeded. Monitoring ambient temperature
does not guarantee that T
J
is within the specified temperature
limits. In applications with high power dissipation and poor
thermal resistance, the maximum ambient temperature may
have to be derated.
In applications with moderate power dissipation and low PCB
thermal resistance, the maximum ambient temperature can
exceed the maximum limit as long as the junction temperature
is within specification limits. The junction temperature (T
J
) of
the device is dependent on the ambient temperature (T
A
), the
power dissipation of the device (P
D
), and the junction-to-ambient
thermal resistance of the package (θ
JA
).
The maximum junction temperature (T
J
) is calculated from the
ambient temperature (T
A
) and power dissipation (P
D
) using the
formula
T
J
=
T
A
+ (P
D
×
θ
JA
)
The junction-to-ambient thermal resistance (θ
JA
) of the package
is based on modeling and calculation using a 4-layer board. The
junction-to-ambient thermal resistance is highly dependent
on the application and board layout. In applications where high
maximum power dissipation exists, close attention to thermal
board design is required. The value of θ
JA
may vary, depending
THERMAL RESISTANCE
θ
JA
and Ψ
JB
are specified for the worst-case conditions, that is, a
device soldered in a circuit board for surface-mount packages.
