Synchronous Current-Mode with
Constant On-Time, PWM Buck Controller
Data Sheet
FEATURES
Power input voltage as low as 2.75 V to 20 V
Bias supply voltage range: 2.75 V to 5.5 V
Minimum output voltage: 0.6 V
0.6 V reference voltage with ±1.0% accuracy
Supports all N-channel MOSFET power stages
Available in 300 kHz, 600 KHz, and 1.0 MHz options
No current-sense resistor required
Power saving mode (PSM) for light loads (ADP1873 only)
Resistor-programmable current-sense gain
Thermal overload protection
Short-circuit protection
Precision enable input
Integrated bootstrap diode for high-side drive
140 µA shutdown supply current
Starts into a precharged load
Small, 10-lead MSOP package
EFFICIENCY (%)
ADP1872/ADP1873
TYPICAL APPLICATIONS CIRCUIT
V
IN
= 2.75V TO 20V
C
C
R
C
V
OUT
R
TOP
FB
R
BOT
GND
C
VDD2
V
DD
= 2.75V
TO 5.5V
C
VDD
VDD
PGND
SW
DRVL
R
RES
08297-001
VIN
C
C2
ADP1872/
ADP1873
COMP/EN
BST
C
BST
DRVH
C
IN
Q1
L
V
OUT
+
C
OUT
Q2
LOAD
5A
Figure 1.
100
V
DD
= 5.5V, V
IN
= 5.5V (PSM)
95
90
85
80
75
70
65
60
55
50
45
100
1k
V
DD
= 5.5V, V
IN
= 16.5V (PSM)
V
DD
= 5.5V, V
IN
= 13.0V (PSM)
V
DD
= 5.5V, V
IN
= 5.5V
APPLICATIONS
Telecom and networking systems
Mid to high end servers
Set-top boxes
DSP core power supplies
T
A
= 25°C
V
OUT
= 1.8V
f
SW
= 300kHz
WURTH INDUCTOR:
744325120, L = 1.2µH, DCR = 1.8mΩ
INFINEON FETs:
BSC042N03MS G (UPPER/LOWER)
10k
100k
08297-002
LOAD CURRENT (mA)
Figure 2. ADP1872 Efficiency vs. Load Current (V
OUT
= 1.8 V, 300 kHz)
GENERAL DESCRIPTION
The ADP1872/ADP1873 are versatile current-mode, synchronous
step-down controllers that provide superior transient response,
optimal stability, and current limit protection by using a constant
on-time, pseudo-fixed frequency with a programmable current-
sense gain, current-control scheme. In addition, these devices offer
optimum performance at low duty cycles by using valley current-
mode control architecture. This allows the ADP1872/ADP1873
to drive all N-channel power stages to regulate output voltages
as low as 0.6 V.
The ADP1873 is the power saving mode (PSM) version of the
device and is capable of pulse skipping to maintain output
regulation while achieving improved system efficiency at light
loads (see the Power Saving Mode (PSM) Version (ADP1873)
section for more information).
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
Available in three frequency options (300 kHz, 600 kHz, and
1.0 MHz, plus the PSM option), the ADP1872/ADP1873 are
well suited for a wide range of applications. These ICs not only
operate from a 2.75 V to 5.5 V bias supply, but can also accept a
power input as high as 20 V.
In addition, an internally fixed, soft start period is included to limit
input in-rush current from the input supply during startup and
to provide reverse current protection during soft start for a pre-
charged output. The low-side current-sense, current-gain scheme
and integration of a boost diode, along with the PSM/forced pulse-
width modulation (PWM) option, reduce the external part count
and improve efficiency.
The ADP1872/ADP1873 operate over the −40°C to +125°C
junction temperature range and are available in a 10-lead MSOP.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2009–2012 Analog Devices, Inc. All rights reserved.
ADP1872/ADP1873
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Typical Applications Circuit............................................................ 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Absolute Maximum Ratings............................................................ 5
Thermal Resistance ...................................................................... 5
Boundary Condition .................................................................... 5
ESD Caution .................................................................................. 5
Pin Configuration and Function Descriptions ............................. 6
Typical Performance Characteristics ............................................. 7
ADP1872/ADP1873 Block Digram.............................................. 17
Theory of Operation ...................................................................... 18
Startup .......................................................................................... 18
Soft Start ...................................................................................... 18
Precision Enable Circuitry ........................................................ 18
Undervoltage Lockout ............................................................... 18
Thermal Shutdown..................................................................... 18
Programming Resistor (RES) Detect Circuit .......................... 19
Valley Current-Limit Setting .................................................... 19
Hiccup Mode During Short Circuit ......................................... 20
Synchronous Rectifier ................................................................ 21
Power Saving Mode (PSM) Version (ADP1873) .................... 21
Data Sheet
Timer Operation ........................................................................ 21
Pseudo-Fixed Frequency ........................................................... 22
Applications Information .............................................................. 23
Feedback Resistor Divider ........................................................ 23
Inductor Selection ...................................................................... 23
Output Ripple Voltage (ΔV
RR
) .................................................. 23
Output Capacitor Selection....................................................... 23
Compensation Network ............................................................ 24
Efficiency Consideration ........................................................... 25
Input Capacitor Selection .......................................................... 26
Thermal Considerations............................................................ 27
Design Example .......................................................................... 27
External Component Recommendations .................................... 30
Layout Considerations ................................................................... 32
IC Section (Left Side of Evaluation Board) ............................. 37
Power Section ............................................................................. 37
Differential Sensing .................................................................... 37
Typical Application Circuits ......................................................... 38
Dual-Input, 300 kHz High Current Application Circuit ...... 38
Single-Input, 600 kHz Application Circuit ............................. 38
Dual-Input, 300 kHz High Current Application Circuit ...... 39
Outline Dimensions ....................................................................... 40
Ordering Guide .......................................................................... 40
REVISION HISTORY
7/12—Rev. A to Rev. B
Changed R
ON
= 15 mΩ/100 kΩ Valley Current Level Value from
7.5 to 3.87; Table 6 .......................................................................... 20
Changes to Ordering Guide .......................................................... 40
3/10—Rev. 0 to Rev. A
Changes to Figure 1 .......................................................................... 1
Changes to Table 1 ............................................................................ 3
Changes to Table 2 ............................................................................ 5
Changes to Figure 59 Caption and Figure 60 Caption .............. 16
Changes to Figure 64 ...................................................................... 17
Changes to Timer Operation Section .......................................... 22
Changes to Table 7 .......................................................................... 23
Changes to Inductor Section ......................................................... 28
Changes to Table 9.......................................................................... 31
Changes to Figure 82...................................................................... 32
Changes to Figure 83...................................................................... 33
Changes to Figure 84...................................................................... 34
Changes to Figure 85...................................................................... 35
Changes to Figure 86...................................................................... 36
Changes to Differential Sensing Section and Figure 88 ............ 37
Changes to Figure 89 and Figure 90............................................. 38
Changes to Figure 91...................................................................... 39
Updated Outline Dimensions ....................................................... 40
10/09—Revision 0: Initial Version
Rev. B | Page 2 of 40
Data Sheet
SPECIFICATIONS
ADP1872/ADP1873
All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC). VDD = 5 V,
BST − SW = 5 V, VIN = 13 V. The specifications are valid for T
J
= −40°C to +125°C, unless otherwise specified.
Table 1.
Parameter
POWER SUPPLY CHARACTERISTICS
High Input Voltage Range
Symbol
VIN
Conditions
ADP1872ARMZ-0.3/ADP1873ARMZ-0.3 (300 kHz)
ADP1872ARMZ-0.6/ADP1873ARMZ-0.6 (600 kHz)
ADP1872ARMZ-1.0/ADP1873ARMZ-1.0 (1.0 MHz)
C
IN
= 1 µF to PGND, C
IN
= 0.22 µF to GND
ADP1872ARMZ-0.3/ADP1873ARMZ-0.3 (300 kHz)
ADP1872ARMZ-0.6/ADP1873ARMZ-0.6 (600 kHz)
ADP1872ARMZ-1.0/ADP1873ARMZ-1.0 (1.0 MHz)
FB = 1.5 V, no switching
COMP/EN < 285 mV
Rising VDD (See Figure 34 for temperature variation)
Falling VDD from operational state
See Figure 57
V
FB
T
J
= 25°C
T
J
= −40°C to +85°C
T
J
= −40°C to +125°C
FB = 0.6 V, COMP/EN = released
RES = 47 kΩ ± 1%
RES = 22 kΩ ± 1%
RES = none
RES = 100 kΩ ± 1%
Typical values measured at 50% time points with
0 nF at DRVH and DRVL; maximum values are
guaranteed by bench evaluation
1
2.7
5.5
11
22
Min
2.75
2.75
3.0
2.75
2.75
3.0
Typ
12
12
12
5
5
5
1.1
140
2.65
190
3.0
600
600
600
515
1
3
6
12
24
Max
20
20
20
5.5
5.5
5.5
215
Unit
V
V
V
V
V
V
mA
µA
V
mV
ms
mV
mV
mV
µs
nA
V/V
V/V
V/V
V/V
Low Input Voltage Range
VDD
Quiescent Current
Shutdown Current
Undervoltage Lockout
UVLO Hysteresis
SOFT START
Soft Start Period
ERROR AMPLIFER
FB Regulation Voltage
I
Q_DD
+ I
Q_BST
I
DD, SD
+ I
BST, SD
UVLO
Transconductance
FB Input Leakage Current
CURRENT-SENSE AMPLIFIER GAIN
Programming Resistor (RES)
Value from DRVL to PGND
G
M
I
FB, LEAK
595.5
594.2
300
605.4
606.5
730
50
3.3
6.5
13
26
SWITCHING FREQUENCY
ADP1872ARMZ-0.3/
ADP1873ARMZ-0.3 (300 kHz)
On-Time
Minimum On-Time
Minimum Off-Time
ADP1872ARMZ-0.6/
ADP1873ARMZ-0.6 (600 kHz)
On-Time
Minimum On-Time
Minimum Off-Time
ADP1872ARMZ-1.0/
ADP1873ARMZ-1.0 (1.0 MHz)
On-Time
Minimum On-Time
Minimum Off-Time
300
VIN = 5 V, V
OUT
= 2 V, T
J
= 25°C
VIN = 20 V
84% duty cycle (maximum)
1120
1200
145
320
600
520
82
320
1.0
312
60
320
1280
190
385
kHz
ns
ns
ns
kHz
ns
ns
ns
MHz
ns
ns
ns
VIN = 5 V, V
OUT
= 2 V, T
J
= 25°C
VIN = 20 V, V
OUT
= 0.8 V
65% duty cycle (maximum)
500
580
110
385
VIN = 5 V, V
OUT
= 2 V, T
J
= 25°C
VIN = 20 V
45% duty cycle (maximum)
285
340
85
385
Rev. B | Page 3 of 40
ADP1872/ADP1873
Parameter
OUTPUT DRIVER CHARACTERISTICS
High-Side Driver
Output Source Resistance
Output Sink Resistance
Rise Time
2
Fall Time
2
Low-Side Driver
Output Source Resistance
Output Sink Resistance
Rise Time
2
Fall Time
2
Propagation Delays
DRVL Fall to DRVH Rise
2
DRVH Fall to DRVL Rise
2
SW Leakage Current
Integrated Rectifier
Channel Impedance
PRECISION ENABLE THRESHOLD
Logic High Level
Enable Hysteresis
COMP VOLTAGE
COMP Clamp Low Voltage
COMP Clamp High Voltage
COMP Zero Current Threshold
THERMAL SHUTDOWN
Thermal Shutdown Threshold
Thermal Shutdown Hysteresis
Hiccup Current Limit Timing
1
Data Sheet
Symbol
Conditions
Min
Typ
Max
Unit
t
r, DRVH
t
f, DRVH
I
SOURCE
= 1.5 A, 100 ns, positive pulse (0 V to 5 V)
I
SINK
= 1.5 A, 100 ns, negative pulse (5 V to 0 V)
BST − SW = 4.4 V, C
IN
= 4.3 nF (see Figure 59)
BST − SW = 4.4 V, C
IN
= 4.3 nF (see Figure 60)
I
SOURCE
= 1.5 A, 100 ns, positive pulse (0 V to 5 V)
I
SINK
= 1.5 A, 100 ns, negative pulse (5 V to 0 V)
VDD = 5.0 V, C
IN
= 4.3 nF (see Figure 60)
VDD = 5.0 V, C
IN
= 4.3 nF (see Figure 59)
BST − SW = 4.4 V (see Figure 59)
BST − SW = 4.4 V (see Figure 60)
BST = 25 V, SW = 20 V, VDD = 5.5 V
I
SINK
= 10 mA
VIN = 2.9 V to 20 V, VDD = 2.75 V to 5.5 V
VIN = 2.9 V to 20 V, VDD = 2.75 V to 5.5 V
235
2
0.8
25
11
1.7
0.75
18
16
22
24
3.5
2
Ω
Ω
ns
ns
Ω
Ω
ns
ns
ns
ns
µA
Ω
3
2
t
r, DRVL
t
f, DRVL
t
tpdh, DRVH
t
tpdh, DRVL
I
SW, LEAK
110
22
285
35
330
mV
mV
V
V
COMP (LOW)
V
COMP (HIGH)
V
COMP_ZCT
T
TMSD
From disable state, release COMP/EN pin to enable
device (2.75 V ≤ VDD ≤ 5.5 V)
(2.75 V ≤ VDD ≤ 5.5 V)
(2.75 V ≤ VDD ≤ 5.5 V)
Rising temperature
0.47
2.55
1.15
155
15
6
V
V
°C
°C
ms
The maximum specified values are with the closed loop measured at 10% to 90% time points (see Figure 59 and Figure 60), C
GATE
= 4.3 nF and upper- and lower-side
MOSFETs being Infineon BSC042N03MS G.
2
Not automatic test equipment (ATE) tested.
Rev. B | Page 4 of 40
Data Sheet
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter
VDD to GND
VIN to PGND
FB, COMP/EN to GND
DRVL to PGND
SW to PGND
SW to PGND
BST to SW
BST to PGND
DRVH to SW
PGND to GND
Operating Junction Temperature
Range
Storage Temperature Range
Soldering Conditions
Maximum Soldering Lead
Temperature (10 sec)
Rating
−0.3 V to +6 V
−0.3 V to +28 V
−0.3 V to (VDD + 0.3 V)
−0.3 V to (VDD + 0.3 V)
−0.3 V to +28 V
−2 V pulse (20 ns)
−0.6 V to (VDD + 0.3 V)
−0.3 V to +28 V
−0.3 V to VDD
±0.3 V
−40°C to +125°C
−65°C to +150°C
JEDEC J-STD-020
300°C
ADP1872/ADP1873
Absolute maximum ratings apply individually only, not in
combination. Unless otherwise specified, all other voltages are
referenced to PGND.
THERMAL RESISTANCE
θ
JA
is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
Table 3. Thermal Resistance
Package Type
θ
JA
(10-Lead MSOP)
2-Layer Board
4-Layer Board
θ
JA
213.1
171.7
Unit
°C/W
°C/W
BOUNDARY CONDITION
In determining the values given in Table 2 and Table 3, natural
convection was used to transfer heat to a 4-layer evaluation board.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
Rev. B | Page 5 of 40
