Data Sheet
FEATURES
4 A continuous output current
43 mΩ and 29 mΩ integrated FET
±1.5% output accuracy
Input voltage range: 2.7 V to 6.5 V
Output voltage: 0.6 V to V
IN
Switching frequency
Fixed frequency: 600 kHz or 1.2 MHz
Adjustable frequency: 500 kHz to 1.4 MHz
Synchronizable from 500 kHz to 1.4 MHz
Selectable synchronize phase shift: 0° or 180°
Current mode architecture
Precision enable input
Power-good output
Voltage tracking input
Integrated soft start
Internal compensation
Starts up into a precharged output
UVLO, OVP, OCP, and thermal shutdown
Available in 16-lead, 4 mm × 4 mm LFCSP package
6.5 V, 4 A, High Efficiency,
Step-Down DC-to-DC Regulator
ADP2164
TYPICAL APPLICATIONS CIRCUIT
R1
R2
PGOOD VIN
EN
SYNC
TRK
RT
R
T
C1
PVIN
L
SW
C
OUT
V
OUT
C
IN
V
IN
ADP2164
FB
PGND
GND
Figure 1.
100
95
90
85
EFFICIENCY (%)
80
75
70
65
60
55
50
0
V
IN
= 5V
f
S
= 600kHz
0.5
1.0
1.5
2.0
2.5
OUTPUT CURRENT (A)
V
OUT
= 1.2V
V
OUT
= 3.3V
3.0
3.5
4.0
09944-002
APPLICATIONS
Point-of-load conversion
Communications and networking equipment
Industrial and instrumentation
Consumer electronics
Figure 2. Efficiency vs. Output Current
GENERAL DESCRIPTION
The
ADP2164
is a 4 A, synchronous, step-down dc-to-dc regulator
in a compact 4 mm × 4 mm LFCSP package. The regulator uses a
current mode, constant frequency pulse-width modulation (PWM)
control scheme for excellent stability and transient response.
The input voltage range of the
ADP2164
is 2.7 V to 6.5 V. The
output voltage of the
ADP2164
is adjustable from 0.6 V to the
input voltage (V
IN
). The
ADP2164
is also available in six preset
output voltage options: 3.3 V, 2.5 V, 1.8 V, 1.5 V, 1.2 V, and 1.0 V.
The
ADP2164
integrates a pair of low on-resistance P-channel
and N-channel internal MOSFETs to maximize efficiency and
minimize external component count. The 100% duty cycle
operation allows low dropout voltage at 4 A output current.
The high, 1.2 MHz PWM switching frequency allows the use of
small external components, and the SYNC input enables multiple
ICs to synchronize out of phase to reduce ripple and eliminate
beat frequencies.
Other key features of the
ADP2164
include undervoltage lockout
(UVLO), integrated soft start to limit inrush current at startup,
overvoltage protection (OVP), overcurrent protection (OCP),
and thermal shutdown.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2011 Analog Devices, Inc. All rights reserved.
09944-001
ADP2164
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Typical Applications Circuit............................................................ 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Absolute Maximum Ratings............................................................ 5
Thermal Resistance ...................................................................... 5
ESD Caution .................................................................................. 5
Pin Configuration and Function Descriptions ............................. 6
Typical Performance Characteristics ............................................. 7
Functional Block Diagram ............................................................ 13
Theory of Operation ...................................................................... 14
Control Scheme .......................................................................... 14
Slope Compensation .................................................................. 14
Precision Enable/Shutdown ...................................................... 14
Data Sheet
Integrated Soft Start ................................................................... 14
Oscillator and Synchronization ................................................ 14
Power Good ................................................................................ 15
Current Limit and Short-Circuit Protection ............................ 15
Overvoltage Protection (OVP) ................................................. 15
Undervoltage Lockout (UVLO) ............................................... 15
Thermal Shutdown .................................................................... 15
Applications Information .............................................................. 16
Output Voltage Selection........................................................... 16
Inductor Selection ...................................................................... 16
Output Capacitor Selection....................................................... 16
Input Capacitor Selection .......................................................... 17
Voltage Tracking ......................................................................... 17
Applications Circuits...................................................................... 18
Outline Dimensions ....................................................................... 19
Ordering Guide .......................................................................... 19
REVISION HISTORY
12/11—Revision 0: Initial Version
Rev. 0 | Page 2 of 20
Data Sheet
SPECIFICATIONS
VIN = PVIN = 3.3 V, EN high, SYNC high, T
J
= −40°C to +125°C, unless otherwise noted. Typical values are at T
J
= 25°C.
Table 1.
Parameter
VIN AND PVIN PINS
VIN Voltage Range
PVIN Voltage Range
Quiescent Current
Shutdown Current
VIN Undervoltage Lockout Threshold
OUTPUT CHARACTERISTICS
Load Regulation
Line Regulation
FB PIN
FB Regulation Voltage
FB Bias Current
SW PIN
High-Side On Resistance
1
Low-Side On Resistance
1
SW Peak Current Limit
SW Maximum Duty Cycle
SW Minimum On Time
2
TRK PIN
TRK Input Voltage Range
TRK to FB Offset Voltage
TRK Input Bias Current
FREQUENCY
Switching Frequency
Symbol
VIN
PVIN
I
VIN
I
SHDN
UVLO
Test Conditions/Comments
Min
2.7
2.7
No switching
VIN = PVIN = 6.5 V, EN = GND
VIN rising
VIN falling
Specified by the circuit in Figure 42
I
O
= 0 A to 4 A
I
O
= 2 A
T
J
= −40°C to +125°C
895
9
2.6
2.5
0.05
0.05
0.591
0.6
0.01
52
43
32
29
6.2
100
0
−15
600
+15
100
1.2
600
600
1.32
660
720
1400
0.45
0.5
100
100
1.2
1.4
0.609
0.1
70
55
40
35
7.4
100
Typ
Max
6.5
6.5
1100
12
2.7
ADP2164
Unit
V
V
μA
μA
V
V
%/A
%/V
V
μA
mΩ
mΩ
mΩ
mΩ
A
%
ns
mV
mV
nA
MHz
kHz
kHz
kHz
V
V
MHz
ns
ns
V
V
%
%
%
%
Clock
cycles
μA
mV
2.4
V
FB
I
FB
VIN = PVIN = 3.3 V, I
SW
= 500 mA
VIN = PVIN = 5 V, I
SW
= 500 mA
VIN = PVIN = 3.3 V, I
SW
= 500 mA
VIN = PVIN = 5 V, I
SW
= 500 mA
High-side switch, PVIN = 3.3 V
Full frequency
Full frequency
35
30
24
20
5
TRK = 0 mV to 500 mV
f
S
RT = VIN
RT = GND
RT = 91 kΩ
Switching Frequency Range
RT Pin Input High Voltage
RT Pin Input Low Voltage
SYNC PIN
Synchronization Range
Minimum Pulse Width
Minimum Off Time
Input High Voltage
Input Low Voltage
PGOOD PIN
Power-Good Range
1.08
540
480
500
1.2
0.4
FB rising threshold
FB rising hysteresis
FB falling threshold
FB falling hysteresis
From FB to PGOOD
V
PGOOD
= 5 V
I
PGOOD
= 1 mA
105
85
110
2.5
90
2.5
16
0.1
170
115
95
Power-Good Deglitch Time
Power-Good Leakage Current
Power-Good Output Low Voltage
1
220
Rev. 0 | Page 3 of 20
ADP2164
Parameter
INTEGRATED SOFT START
Soft Start Time
EN PIN
EN Input Rising Threshold
EN Input Hysteresis
EN Pull-Down Resistor
THERMAL SHUTDOWN
Thermal Shutdown Threshold
Thermal Shutdown Hysteresis
1
2
Data Sheet
Symbol
Test Conditions/Comments
All switching frequencies
Min
Typ
2048
Max
Unit
Clock
cycles
1.28
V
mV
MΩ
°C
°C
1.12
1.2
100
1
140
15
T
J
increasing
Pin-to-pin measurements.
Guaranteed by design.
Rev. 0 | Page 4 of 20
Data Sheet
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter
PVIN, VIN, SW
FB, SYNC, TRK, RT, EN, PGOOD
PGND to GND
Operating Junction Temperature Range
Storage Temperature Range
Soldering Conditions
Rating
−0.3 V to +7 V
−0.3 V to +7 V
−0.3 V to +0.3 V
−40°C to +125°C
−65°C to +150°C
JEDEC J-STD-020
ADP2164
THERMAL RESISTANCE
θ
JA
is measured using natural convection on a JEDEC 4-layer
board. The exposed pad is soldered to the printed circuit board
with thermal vias.
Table 3. Thermal Resistance
Package Type
16-Lead LFCSP
θ
JA
38.3
Unit
°C/W
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
Rev. 0 | Page 5 of 20
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