ADP3208C
7-Bit, Programmable,
Dual-Phase, Mobile, CPU,
Synchronous Buck
Controller
The ADP3208C is a highly efficient, multiphase, synchronous buck
switching regulator controller. With its integrated drivers, the
ADP3208C is optimized for converting the notebook battery voltage
into the core supply voltage required by high performance Intel
processors. An internal 7−bit DAC is used to read a VID code directly
from the processor and to set the CPU core voltage to a value within
the range of 0.3 V to 1.5 V. The phase relationship of the output signals
ensures interleaved 2−phase operation.
The ADP3208C uses a multi−mode architecture run at a
programmable switching frequency and optimized for efficiency
depending on the output current requirement. The ADP3208C
switches between single− and dual−phase operation to maximize
efficiency with all load conditions. The chip includes a programmable
load line slope function to adjust the output voltage as a function of the
load current so that the core voltage is always optimally positioned for
a load transient. The ADP3208C also provides accurate and reliable
short−circuit protection, adjustable current limiting, and a delayed
power−good output. The IC supports On−The−Fly (OTF) output
voltage changes requested by the CPU.
The ADP3208C is specified over the extended commercial
temperature range of
−10°C
to 100°C and is available in a 48−lead
LFCSP.
Features
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LFCSP48
CASE 932AD
MARKING DIAGRAM
ADP3208C
AWLYYWWG
A
WL
YYWW
G
= Assembly Location
= Wafer Lot
= Date Code
= Pb−Free Package
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 36 of this data sheet.
•
Single−Chip Solution
•
Fully Compatible with the Intel
®
IMVP−6+t
•
•
•
•
•
•
•
•
•
•
Specifications
Integrated MOSFET Drivers
Input Voltage Range of 3.3 V to 22 V
Selectable 1− or 2−Phase Operation with Up to 1 MHz
per Phase Switching Frequency
Guaranteed
±8
mV Worst−Case Differentially Sensed
Core Voltage Error Overtemperature
Automatic Power−Saving Mode Maximizes Efficiency
with Light Load During Deeper Sleep Operation
Soft Transient Control Reduces Inrush Current and
Audio Noise
Active Current Balancing Between Output Phases
Independent Current Limit and Load Line Setting
Inputs for Additional Design Flexibility
Built−In Power−Good Blanking Supports Voltage
Identification (VID) OTF Transients
7−Bit, Digitally Programmable DAC with 0.3 V to
1.5 V Output
1
•
Short−Circuit Protection with Latchoff Delay
•
Clock Enable Output Delays the CPU Clock Until the
Core Voltage is Stable
•
Output Load Current Monitor
•
This is a Pb−Free Device
Applications
•
Notebook Power Supplies for Next Generation
Intel
®
Processors
©
Semiconductor Components Industries, LLC, 2010
February, 2010
−
Rev. 0
Publication Order Number:
ADP3208D/D
ADP3208C
GND VCC EN
UVLO
Shutdown
and Bias
+
REF
LLINE
PSI
TTSNS
VRTT
Thermal
Throttle
Control
DAC
−
200mV
CSREF
−
+
−
+
PWRGD
Startup
Delay
OCP
Shutdown
Delay
Current
Limit
Circuit
+
VEA
−
+
CSREF
1.7V
−
+
+
_
OVP
RPM RT RAMP
VARFREQ SP
BST1
Oscillator
Current
Balancing
Circuit
Driver
Logic
DRVH1
SW1
PVCC1
DRVL1
PGND1
BST2
DRVH2
SW2
PVCC2
DRVL2
PGND2
COMP
FB
Σ
Σ
+
DPRSTP
DPRSLP
Logic
Current
Monitor
+
−
DPRSTP
DPRSLP
IMON
DAC
−
300mV
PWRGD
Open
Drain
CLKEN
Open
Drain
PWRGD
CLKEN
Soft
Transient
Delay
CLKEN
Startup
Delay
Delay
Disable
CSREF
CSSUM
CSCOMP
ILIMN
ILIMP
FBRTN
Precision
Reference
VID
DAC
DAC
IREF
VID2
VID1
VID0
REF
Soft−Start
Soft Transient
VID6
VID5
VID4
Figure 1. Functional Block Diagram
ABSOLUTE MAXIMUM RATINGS
Parameter
VCC, PVCC1, PVCC2
FBRTN, PGND1, PGND2
BST1, BST2
DC
t < 200 ns
BST1 to SW1, BST2 to SW2
SW1, SW2
DC
t < 200 ns
DRVH1 to SW1, DRVH2 to SW2
DRVL1 to PGND1, DRVL2 to PGND2
DC
t < 200 ns
RAMP (In Shutdown) DC
All Other Inputs and Outputs
Storage Temperature
Operating Ambient Temperature Range
Operating Junction Temperature
Thermal Impedance (q
JA
) 2−Layer Board
Lead Temperature
Soldering (10 sec)
Infrared (15 sec)
Rating
−0.3
to +6.0
−0.3
to +0.3
−0.3
to +28
−0.3
to +33
−0.3
to +6.0
−5.0
to +22
−10
to +28
−0.3
to +6.0
−0.3
to +6.0
−5.0
to +6.0
−0.3
to +22
−0.3
to +6.0
−65
to +150
−10
to 100
125
40
300
260
Unit
V
V
V
VID3
V
V
V
V
V
V
°C
°C
°C
°C/W
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
NOTE: This device is ESD sensitive. Use standard ESD precautions when handling.
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2
ADP3208C
TEST CIRCUITS
7-BIT CODE
5.0 V
ADP3208C
48
DPRSLP
PSI
VID0
VID1
VID4
VID2
DPRSTP
VID3
VID5
VID6
SP
1
1.05 V
PWRGD
NC
CLKEN#
FB
FBRTN
COMP
1 kW
NC
NC
VARFREQ
VRTT
CSSUM
CSREF
TTSNS
LLINE
IMON
IREF
RPM
CSCOMP
RAMP
ILIMN
ILIMP
EN
VCC
5.0 V
BST1
SW1
37
VCC
DRVH1
PVCC1
DRVL1
17
CSCOMP
ADP3208C
PGND1
PGND2
DRVL2
PVCC2
SW2
DRVH2
BST2
GND
39 k
W
1 kW
100 nF
19
18
CSSUM
CSREF
-
+
1.0 V
24
GND
RT
V
os
=
CSCOMP - 1.0 V
40 V
80 kW
20 kW
100 nF
Figure 2. Closed−Loop Output Voltage Accuracy
Figure 3. Current Sense Amplifier, V
OS
ADP3208C
5.0 V
37
VCC
7
COMP
10 k
W
6
FB
-
+
16
LLINE
Δ
V
18
CSREF
VID DAC
1.0 V
24
GND
D
V
FB
= FB
D
V
= V
−
FB
D
V=0mV
Figure 4. Positioning Accuracy
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3
ADP3208C
PIN FUNCTION DESCRIPTIONS
Pin No
1
2
3
4
5
6
7
8
9
Mnemonic
EN
PWRGD
NC
CLKEN
FBRTN
FB
COMP
NC
IRPM/NC
Description
Enable Input. Driving this pin low shuts down the chip, disables the driver outputs, pulls PWRGD and VRTT
low, and pulls CLKEN high.
Power−Good Output. Open−drain output. A low logic state means that the output voltage is outside of the
VID DAC defined range.
Not Connected.
Clock Enable Output. Open−drain output. A low logic state enables the CPU internal PLL clock to lock to the
external clock.
Feedback Return Input/Output. This pin remotely senses the CPU core voltage. It is also used as the ground
return for the VID DAC and the voltage error amplifier blocks.
Voltage Error Amplifier Feedback Input. The inverting input of the voltage error amplifier.
Voltage Error Amplifier Output and Frequency Compensation Point.
Not Connected.
RPM Mode Timing Control Input. A resistor between this pin or RPM pin to ground sets the RPM mode
turn−on threshold voltage. If a resistor is connected between this pin to ground, RPM pin must remain
floating and not connected.
Variable Frequency Enable Input. A high logic state enables the PWM clock frequency to vary with VID code.
Voltage Regulator Thermal Throttling Output. Logic high state indicates that the voltage regulator
temperature at the remote sensing point exceeded a set alarm threshold level.
Thermal Throttling Sense and Crowbar Disable Input. A resistor divider where the upper resistor is
connected to VCC, the lower resistor (NTC thermistor) is connected to GND, and the center point is
connected to this pin and acts as a temperature sensor half bridge. Connecting TTSNS to GND disables the
thermal throttling function and disables the crowbar, or Overvoltage Protection (OVP), feature of the chip.
Current Monitor Output. This pin sources a current proportional to the output load current. A resistor to
FBRTN sets the current monitor gain.
RPM Mode Timing Control Input. A resistor between this pin or IRPM pin to ground sets the RPM mode
turn−on threshold voltage. If a resistor is connected between this pin to ground, IRPM pin must remain
floating.
This pin sets the internal bias currents. A 80 kW resistor is connected from this pin to ground.
Load Line Programming Input. The center point of a resistor divider connected between CSREF and
CSCOMP can be tied to this pin to set the load line slope.
Current Sense Amplifier Output and Frequency Compensation Point.
Current Sense Reference Input. This pin must be connected to the common point of the output inductors.
The node is shorted to GND through an internal switch when the chip is disabled to provide soft stop
transient control of the converter output voltage.
Current Sense Summing Input. External resistors from each switch node to this pin sum the inductor currents
to provide total current information.
PWM Ramp Slope Setting Input. An external resistor from the converter input voltage node to this pin sets
the slope of the internal PWM stabilizing ramp used for phase−current balancing.
Current Limit Set. An external resistor from ILIMN to ILIMP sets the current limit threshold of the converter.
Current Limit Set. An external resistor from ILIMN to ILIMP sets the current limit threshold of the converter.
PWM Oscillator Frequency Setting Input. An external resistor from this pin to GND sets the PWM oscillator
frequency.
Analog and Digital Signal Ground.
High−Side Bootstrap Supply for Phase 2. A capacitor from this pin to SW2 holds the bootstrapped voltage
while the high−side MOSFET is on.
High−Side Gate Drive Output for Phase 2.
Current Balance Input for Phase 2 and Current Return for High−Side Gate Drive.
Power Supply Input/Output of Low−Side Gate Driver for Phase 2.
Low−Side Gate Drive Output for Phase 2.
Low−Side Driver Power Ground for Phase 2.
10
11
12
VARFREQ
VRTT
TTSNS
13
14
IMON
RPM
15
16
17
18
IREF
LLINE
CSCOMP
CSREF
19
20
21
22
23
24
25
26
27
28
29
30
CSSUM
RAMP
ILIMN
ILIMP
RT
GND
BST2
DRVH2
SW2
PVCC2
DRVL2
PGND2
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4
ADP3208C
Pin No
31
32
33
34
35
36
37
38
39 to
45
46
47
48
Mnemonic
PGND1
DRVL1
PVCC1
SW1
DRVH1
BST1
VCC
SP
VID6 to
VID0
PSI
DPRSTP
DPRSLP
Low−Side Driver Power Ground for Phase 1.
Low−Side Gate Drive Output for Phase 1.
Power Supply Input/Output of Low−Side Gate Driver for Phase 1.
Current Balance Input for Phase 1 and Current Return For High−Side Gate Drive.
High−Side Gate Drive Output for Phase 1.
High−Side Bootstrap Supply for Phase 1. A capacitor from this pin to SW1 holds the bootstrapped voltage
while the high−side MOSFET is on.
Power Supply Input/Output of the Controller.
Single−Phase Select Input. Logic high state sets single−phase configuration.
Voltage Identification DAC Inputs. A 7−bit word (the VID code) programs the DAC output voltage, the
reference voltage of the voltage error amplifier without a load (see the VID code Table 3).
Power State Indicator Input. Driving this pin low forces the controller to operate in single−phase mode.
Deeper Stop Control Input. The logic state of this pin is usually complementary to the state of the DPRSLP
pin; however, during slow deeper sleep exit, both pins are logic low.
Deeper Sleep Control Input.
Description
EN
PWRGD
NC
CLKEN
FBRTN
FB
COMP
NC
IRPM/NC
VARFREQ
VRTT
TTSNS
DPRSLP
DPRSTP
PSI
VID0
VID1
VID2
VID3
VID4
VID5
VID6
SP
VCC
1
ADP3208C
BST1
DRVH1
SW1
PVCC1
DRVL1
PGND1
PGND2
DRVL2
PVCC2
SW2
DRVH2
BST2
IMON
RPM
IREF
LLINE
CSCOMP
CSREF
CSSUM
RAMP
ILIMIN
ILIMP
RT
GND
Figure 5. Pin Configuration
(Top View)
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5
实时操作系统RTOS
