ADP3210
7-Bit, Programmable,
Multiphase Mobile CPU
Synchronous Buck
Controller
The ADP3210 is a high efficiency, multiphase, synchronous,
buck−switching regulator controller optimized for converting
notebook battery voltage into the core supply voltage of high
performance Intel processors. The part uses an internal 7−bit DAC to
read Voltage Identification (VID) code directly from the processor that
sets the output voltage. The phase relationship of the output signals
can be configured for 1−, 2−, or 3−phase operation, with interleaved
switching.
The ADP3210 uses a multi−mode architecture to drive the
logic−level PWM outputs at a switching frequency selected by the
user depending on the output current requirement. The part switches
between multiphase and single−phase operation according to a system
signal provided by the CPU. Shedding phases as function of the load
maximizes power conversion efficiency under different load
conditions. In addition, the ADP3210 supports programmable
load−line resistance adjustment. As a result, the output voltage is
always optimally positioned for a load transient.
The chip also provides accurate and reliable short−circuit protection
with adjustable current limit threshold and a delayed power−good
output that is masked during On−The−Fly (OTF) output voltage
changes to eliminate false alarm.
The ADP3210 performance is specified over the extended
commercial temperature range of
−10°C
to 100°C. The chip is
available in a 40−lead QFN package.
Features
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1 40
QFN40
MN SUFFIX
CASE 488AR
MARKING DIAGRAM
1
ADP3210
AWLYYWWG
A
WL
YY
WW
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
•
•
•
•
•
•
•
•
•
•
•
•
PIN ASSIGNMENT
VID0
VID1
VID2
VID3
VID4
VID5
VID6
PSI
NC
VCC
EN
PWRGD
IMON
CLKEN
FBRTN
FB
COMP
NC
TRDET
DPRSLP
1
40
1−, 2−, or 3−Phase Operation at Up to 1 MHz per Phase
Input Voltage Range of 3.3 V to 22 V
±6
mV Worst−Case Differential Sensing Error Overtemperature
Interleaved PWM Outputs for Driving External High Power
MOSFET Drivers
Automatic Power−Saving Modes Maximize Efficiency During Light
Load and Deeper Sleep Operation
Active Current Balancing Between Output Phases
Independent Current Limit and Load Line Setting Inputs for
Additional Design Flexibility
7−Bit Digitally Programmable 0 V to 1.5 V Output
Overload and Short−Circuit Protection with Latchoff Delay
Built−In Clock Enable Output for Delaying CPU Clock
Synchronization Until CPU Supply Voltage Stabilizes
Output Current Monitor
This is a Pb−Free Device
ADP3210
(top view)
TTSN
VRTT
DCM1
OD
PWM1
PWM2
PWM3
SW1
SW2
SW3
Applications
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 31 of this data sheet.
•
Notebook Power Supplies for Next Generation Intel
®
Processors
©
Semiconductor Components Industries, LLC, 2011
November, 2011
−
Rev. 2
1
ILIM
IREF
RPM
RT
RAMP
LLINE
CSREF
CSSUM
CSCOMP
GND
Publication Order Number:
ADP3210/D
ADP3210
GND
VCC EN
RPM
RT
RAMP
PWM1
Oscillator
Driver
Logic
PWM2
PWM3
DCM1
TRDET
COMP
FB
TRDET
Generator
UVLO
Shutdown
and Bias
VEA
-
REF
+
+
Σ
Σ
Σ
Σ
+
+
CSREF
OVP
+
1.55 V
PSI and
DPRSLP
Logic
Current
Balancing
Circuit
LLINE
PSI
DPRSLP
OD
SW1
SW2
SW3
OCP
Shutdown
Delay
Current
Monitor
Current
Limit
Circuit
IMON
DAC + 200 mV
-
CSREF
+
-
+
DAC - 300 mV
PWRGD
Open
Drain
PWRGD
Startup
Delay
Soft
Transient
Delay
CLKEN
Startup
Delay
Delay
Disable
PWRGD
CLKEN
CLKEN
Open
Drain
Precision
Reference
VID
DAC
Thermal
Throttle
Control
Soft-Start
and Soft
Transient
Control
FBRTN
DAC
IREF
VID6
VID5
VID4
VID3
VID2
VID1
VID0
REF
Figure 1. Functional Block Diagram
ABSOLUTE MAXIMUM RATINGS
Parameter
V
CC
FBRTN
SW1 to SW3
DC
t < 200 ns
RAMPADJ (in Shutdown)
All Other Inputs and Outputs
Storage Temperature Range
Operating Ambient Temperature Range
Operating Junction Temperature
Thermal Impedance (q
JA
)
Lead Temperature
Soldering (10 sec)
Infrared (15 sec)
Rating
−0.3
to +6.0
−0.3
to +0.3
−1.0
to +22
−6.0
to +28
−0.3
to +22
−0.3
to V
CC
to +22
−65
to +150
−10
to 100
125
98
300
260
Unit
V
V
V
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
NOTE: This device is ESD sensitive. Use standard ESD precautions when handling.
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2
+
-
-
-
CSREF
CSSUM
CSCOMP
ILIM
TTSENSE
VRTT
V
V
°C
°C
°C
°C/W
°C
ADP3210
PIN FUNCTION DESCRIPTIONS
Pin No.
1
2
3
4
5
6
7
8
9
Mnemonic
EN
PWRGD
IMON
CLKEN
FBRTN
FB
COMP
NC
TRDET
Description
Power Supply Enable Input. Pulling this pin to GND disables the PWM outputs and pulls the PWRGD
output low.
Power−Good Output. Open drain output that signals when the output voltage is outside of the proper
operating range. The pull−high voltage on this pin cannot be higher than VCC.
Current Monitor Output. This pin sources a current proportional to the output load current. A resistor to
FBRTN sets the current monitor gain.
Clock Enable Output. The pull−high voltage on this pin cannot be higher than VCC.
Feedback Return. VID DAC and error amplifier reference for remote sensing of the output voltage.
Feedback Input. Error amplifier input for remote sensing of the output voltage.
Error Amplifier Output and Compensation Point.
Not Connected.
Transient Detect Output. This pin is pulled low when a load release transient is detected. A capacitor to
ground is connected to TRDET pin and a resistor from FB pin to TRDET is connected. During repetitive
load transients at high frequencies, this circuit optimally positions the maximum and minimum output
voltage into a specified load−line window.
Deeper Sleep Control Input.
Current Limit Set−point. An external resistor from this pin to CSCOMP sets the current limit threshold of the
converter.
This pin sets the internal bias currents. A 80kW resistor is connected from this pin to ground.
RPM Mode Timing Control Input. A resistor between this pin to ground sets the RPM mode turn−on
threshold voltage.
Multiphase Frequency Setting Input. An external resistor connected between this pin and GND sets the
oscillator frequency of the device when operating in multiphase PWM mode.
PWM Ramp Current Input. An external resistor from the converter input voltage to this pin sets the internal
PWM ramp.
Output Load Line Programming Input. The center point of a resistor divider between CSREF and CSCOMP
is connected to this pin to set the load line slope.
Current Sense Reference Voltage Input. The voltage on this pin is used as the reference for the current
sense amplifier and the power−good and crowbar functions. This pin should be connected to the common
point of the output inductors.
Current Sense Summing Node. External resistors from each switch node to this pin sum the inductor
currents together to measure the total output current.
Current Sense Compensation Point. A resistor and capacitor from this pin to CSSUM determine the gain of
the current sense amplifier and the positioning loop response time.
Ground. All internal biasing and the logic output signals of the device are referenced to this ground.
Current Balance Inputs. Inputs for measuring the current level in each phase. The SW pins of unused
phases should be left open.
Logic−Level PWM Outputs. Each output is connected to the input of an external MOSFET driver such as
the ADP3419. Connecting the PWM2 and/or PWM3 outputs to VCC causes that phase to turn off, allowing
the ADP3210 to operate as a 1−, 2−, or 3−phase controller.
Multiphase Output Disable Logic Output. This pin is actively pulled low when the ADP3210 enters
single−phase mode or during shutdown. Connect this pin to the SD inputs of the Phase−2 and Phase−3
MOSFET drivers.
Discontinuous Current Mode Enable Output 1. This pin actively pulled low when the single−phase inductor
current crosses zero.
Voltage Regulator Thermal Throttling Logic Output. This pin goes high if the temperature at the monitoring
point connected to TTSN exceeds the programmed VRTT temperature threshold.
Thermal Throttling Sense Input. The center point of a resistor divider (where the lower resistor is an NTC
thermistor) between VCC and GND is connected to this pin to remotely sense the temperature at the
desired thermal monitoring point. Connect TTSN to VCC if this function is not used.
Supply Voltage for the Device.
Not Connected.
Power State Indicator Input. Pulling this pin to GND forces the ADP3210 to operate in single−phase mode.
Voltage Identification DAC Inputs. When in normal operation mode, the DAC output programs the FB
regulation voltage from 0.3 V to 1.5 V.
10
11
12
13
14
15
16
17
DPRSLP
ILIM
IREF
RPM
RT
RAMP
LLINE
CSREF
18
19
20
21 to 23
24 to 26
CSSUM
CSCOMP
GND
SW3 to SW1
PWM3 to
PWM1
OD
27
28
29
30
DCM1
VRTT
TTSN
31
32
33
34 to 40
VCC
NC
PSI
VID6 to VID0
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3
ADP3210
ELECTRICAL CHARACTERISTICS
V
CC
= 5.0 V, FBRTN = GND, EN = V
CC
, V
VID
= 1.20 V to 1.500 V, PSI = 1.1 V, DPRSLP = GND,
LLINE = CSREF, Current going into pin is positive. T
A
=
−10°C
to 100°C, unless otherwise noted. (Note 1) R
REF
= 80 kW
Parameter
FB, LLINE Voltage Range
(Note 2)
FB, LLINE Offset Voltage
(Note 2)
FB Bias Current
LLINE Bias Current
LLINE Positioning Accuracy
COMP Voltage Range
(Note 2)
COMP Current (Note 2)
Symbol
V
FB
, V
LLINE
V
OSVEA
I
FB
I
LL
V
FB
−
V
VID
V
COMP
I
COMP
COMP = 2.0 V, CSREF = V
DAC
FB forced 80 mV below CSREF
FB forced 80 mV above CSREF
C
COMP
= 10 pF, CSREF = V
DAC
FB forced 200 mV below CSREF
FB forced 200 mV above CSREF
Inverting unit gain configuration, R = 1 kW
See VID Code Table
V
FB
−
V
VID
Measured on FB (includes offset), relative
to V
VID
: V
VID
= 0.3000 V to 1.2000 V
V
VID
= 1.2125 V to 1.5000 V
V
CC
= 4.75 V to 5.25 V
Measured during boot delay period
Measured from EN pos edge to FB settles to
V
BOOT
= 1.1 V within 5%
Measured from FB settling to V
BOOT
= 1.1 V
within 5% to CLKEN neg edge
Soft−Start
Non−LSB VID step
D
VID
transition (LSB VID step)
I
FBRTN
V
UVCSREF
V
OVCSREF
V
CBCSREF
V
RVCSREF
Relative to nominal DAC Voltage
Relative to nominal DAC Voltage
Relative to FBRTN
Relative to FBRTN
CSREF Falling
CSREF Rising
I
PWRGD(SINK)
= 4 mA
V
PWRDG
= 5.0 V
Measured from CLKEN neg edge to PWRGD
Pos Edge
Measured from Out−off−Good−Window event
to PWRGD neg edge
8.0
200
−360
135
1.5
0
−6.0
−7.0
−1.0
0.05
1.100
1.4
100
0.0625
1.0
0.4
−90
−300
200
1.55
200
−240
250
1.6
Measured on FB relative to V
VID
,
LLINE forced 80 mV below CSREF
Conditions
Relative to CSREF = V
DAC
Relative to CSREF = V
DAC
Min
−200
−0.5
−1.0
−50
−82
0.85
−80
VOLTAGE CONTROL
−
Voltage Error Amplifier (VEAMP)
+200
+0.5
1.0
50
−78
4.0
mV
mV
mA
nA
mV
V
mA
Typ
Max
Units
−0.75
10
15
−20
20
1.5
+6.0
+7.0
+1.0
COMP Slew Rate (Note 2)
SR
COMP
V/ms
Gain Bandwidth (Note 2)
VID DAC VOLTAGE REFERENCE
V
DAC
Voltage Range (Note 2)
V
DAC
Accuracy
GBW
MHz
V
mV
V
DAC
Differential Non−linearity (Note 2)
V
DAC
Line Regulation
(Note 2)
V
DAC
Boot Voltage
Soft−Start Delay
Boot Delay
V
DAC
Slew Rate
DV
FB
V
BOOTFB
t
SS
t
BOOT
LSB
%
V
ms
ms
LSB/ms
FBRTN Current
CSREF Undervoltage
Threshold
CSREF Overvoltage
Threshold
CSREF Crowbar Voltage
Threshold
CSREF Reverse Voltage
Threshold
PWRGD Low Voltage
PWRGD Leakage Current
PWRGD Startup Delay
PWRGD Propagation Delay
(Note 2)
mA
mV
mV
V
mV
VOLTAGE MONITORING AND PROTECTION
−
Power Good
−350
−300
−75
85
−10
250
1.0
mV
mA
ms
ns
V
PWRGD
I
PWRGD
T
SSPWRGD
T
PDPWRGD
1. All limits at temperature extremes are guaranteed via correlation using standard Statistical Quality Control (SQC).
2. Guaranteed by design or bench characterization, not production tested.
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4
ADP3210
ELECTRICAL CHARACTERISTICS
V
CC
= 5.0 V, FBRTN = GND, EN = V
CC
, V
VID
= 1.20 V to 1.500 V, PSI = 1.1 V, DPRSLP = GND,
LLINE = CSREF, Current going into pin is positive. T
A
=
−10°C
to 100°C, unless otherwise noted. (Note 1) R
REF
= 80 kW
Parameter
PWRGD Masking Time
CSREF Soft−Stop Resistance
CSSUM, CSREF Common−Mode Range (Note 2)
CSSUM, CSREF Offset
Voltage
CSSUM Bias Current
CSREF Bias Current
CSCOMP Current
V
OSCSA
I
BCSSUM
I
BCSREF
CSCOMP = 2.0 V
CSSUM forced 200 mV below CSREF
CSSUM forced 200 mV above CSREF
C
CSCOMP
= 10 pF
CSSUM forced 200 mV below CSREF
CSSUM forced 200 mV above CSREF
GBW
CSA
Inverting unit gain configuration R = 1 kW
CSREF
−
CSSUM, T
A
= 25°C
T
A
=
−10°C
to 85°C
Symbol
Conditions
Triggered by any VID change or OCP event
EN = L or Latchoff condition
0.05
−0.3
−1.2
−50
−1.0
0.05
−660
1.0
10
−10
20
Min
VOLTAGE MONITORING AND PROTECTION
−
Power Good
100
50
3.5
+0.3
+1.2
+50
+1.0
2.0
ms
W
V
mV
nA
mA
V
mA
mA
V/ms
Typ
Max
Units
CURRENT CONTROL
−
Current Sense Amplifier (CSAMP)
CSCOMP Voltage Range (Note NO TAG)
I
CSCOMPsource
I
CSCOMPsink
CSCOMP Slew Rate
(Note 2)
Gain Bandwidth (Note 2)
Current Reference
I
REF
Voltage
Current Limiter (OCP)
Current Limit Threshold
MHz
CURRENT MONITORING AND PROTECTION
V
REF
V
LIMTH
R
REF
= 80 kW to set I
REF
= 20
mA
CSCOMP relative to CSREF, R
LIM
= 4.5 kW,
3−ph configuration, PSI = H
3−ph configuration, PSI = L
2−ph configuration, PSI = H
2−ph configuration, PSI = L
1−ph configuration
1.55
1.6
1.65
V
mV
−70
−15
−70
−30
−70
−90
−30
−90
−45
−90
8.0
I
MON
/I
LIM
Measured from I
LIM
to I
MON
I
LIM
=
−20
mA
I
LIM
=
−10
mA
I
LIM
=
−5
mA
(Note 2)
Relative to FBRTN, I
LIM
=
−30
mA
R
T
= 125 kW, V
VID
= 1.4000 V
See also V
RT
(V
VID
) formula
−110
−50
−110
−65
−110
ms
−
Current Limit Latchoff Delay
CURRENT MONITOR
Current Gain Accuracy
9.4
9.1
8.9
1.0
1.08
0.3
T
A
= +25°C, V
VID
= 1.2000 V
R
T
= 73 kW (Note 2)
R
T
= 125 kW (Note 2)
R
T
= 180 kW
EN = High, I
RAMP
= 60
mA
EN = Low
EN = High
EN = Low, RAMP = 19 V
V
OSRPM
= V
RAMP
−
V
COMP
10
10
10
10.7
11.0
11.4
1.15
I
MON
Clamp Voltage
R
T
Voltage
PWM Clock Frequency
Range (Note 2)
PWM Clock Frequency
V
MAXMON
V
RT
f
CLK
f
CLK
V
V
MHz
kHz
PULSE WIDTH MODULATOR
−
Clock Oscillator
1.2
1.32
3.0
1000
700
500
0.9
1.0
−0.5
−3.0
1300
800
600
1.0
V
IN
1600
900
780
1.1
100
+0.5
3.0
RAMP GENERATOR
RAMP Voltage
RAMP Current Range
(Note 2)
PWM COMPARATOR
PWM Comparator Offset
(Note 2)
V
OSRPM
mV
V
RAMP
I
RAMP
V
mA
1. All limits at temperature extremes are guaranteed via correlation using standard Statistical Quality Control (SQC).
2. Guaranteed by design or bench characterization, not production tested.
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5
