D ts e t
aa h e
R c e t r lc r nc
o h se Ee to is
Ma u a t r dCo o e t
n fc u e
mp n n s
R c e tr b a d d c mp n ns ae
o h se rn e
o oet r
ma ua trd u ig ete dewaes
n fcue sn i r i/ fr
h
p rh s d f m te oiia s p l r
uc a e r
o h r n l u pi s
g
e
o R c e tr waes rce td f m
r o h se
fr e rae r
o
te oiia I. Al rce t n ae
h
r nl P
g
l e rai s r
o
d n wi tea p o a o teOC
o e t h p rv l f h
h
M.
P r aetse u igoiia fcoy
at r e td sn r n la tr
s
g
ts p o rmso R c e tr e eo e
e t rga
r o h se d v lp d
ts s lt n t g aa te p o u t
e t oui s o u rne
o
rd c
me t o e c e teOC d t s e t
es r x e d h
M aa h e.
Qu l yOv riw
ai
t
e ve
• IO- 0 1
S 90
•A 92 cr ct n
S 1 0 et ai
i
o
• Qu l e Ma ua trr Ls (
ai d
n fcues it QML MI- R -
) LP F
385
53
•C a sQ Mitr
ls
lay
i
•C a sVS a eL v l
ls
p c ee
• Qu l e S p l r Ls o D sr uos( L )
ai d u pi s it f it b tr QS D
e
i
•R c e trsacic l u pir oD A a d
o h se i
r ia s p l t L n
t
e
me t aln u t a dD A sa d r s
es lid sr n L tn ad .
y
R c e tr lcrnc , L i c mmi e t
o h se Ee t is L C s o
o
tdo
t
s p ligp o u t ta s t f c so r x e t-
u pyn rd cs h t ai y u tme e p ca
s
t n fr u lya daee u loto eoiial
i s o q ai n r q a t h s r n l
o
t
g
y
s p l db id sr ma ua trr.
u pi
e yn ut
y n fcues
T eoiia ma ua trr d ts e t c o a yn ti d c me t e e t tep r r n e
h r n l n fcue’ aa h e a c mp n ig hs o u n r cs h ef ma c
g
s
o
a ds e ic t n o teR c e tr n fcue v rino ti d vc . o h se Ee t n
n p c ai s f h o h se ma ua trd eso f hs e ie R c e tr lcr -
o
o
isg aa te tep r r n eo i s mio d co p o u t t teoiia OE s e ic -
c u rne s h ef ma c ft e c n u tr rd cs o h r n l M p c a
o
s
g
t n .T pc lv le aefr eee c p r o e o l. eti mii m o ma i m rt g
i s ‘y ia’ au s r o rfrn e up s s ny C r n nmu
o
a
r xmu ai s
n
ma b b s do p o u t h rceiain d sg , i lt n o s mpetsig
y e a e n rd c c aa tr t , e in smuai , r a l e t .
z o
o
n
© 2 1 R cetr l t n s LC Al i t R sre 0 1 2 1
0 3 ohs E cr i , L . lRg s eevd 7 1 0 3
e e oc
h
T l r m r, l s v iw wrcl . m
o e n oe p ae it w . e c o
a
e
s
o ec
a
FEATURES
All-In-One Synchronous Buck Driver
Bootstrapped High Side Drive
One PWM Signal Generates Both Drives
Anticross-Conduction Protection Circuitry
Pulse-by-Pulse Disable Control
APPLICATIONS
Multiphase Desktop CPU Supplies
Mobile Computing CPU Core Power Converters
Single-Supply Synchronous Buck Converters
Standard-to-Synchronous Converter Adaptations
Dual Bootstrapped MOSFET Driver
with Output Disable
ADP3413
FUNCTIONAL BLOCK DIAGRAM
VCC
BST
IN
OVERLAP
PROTECTION
CIRCUIT
OD
3
DRVH
SW
DRVL
ADP3413
GENERAL DESCRIPTION
PGND
The ADP3413 is a dual MOSFET driver optimized for driving
two N-channel MOSFETs which are the two switches in a
nonisolated synchronous buck power converter. Each of the
drivers is capable of driving a 3000 pF load with a 20 ns propa-
gation delay and a 30 ns transition time. One of the drivers can
be bootstrapped and is designed to handle the high voltage
slew rate associated with “floating” high side gate drivers.
The ADP3413 includes overlapping drive protection (ODP)
to prevent shoot-through current in the external MOSFETs.
The
OD
Pin provides high speed control to quickly turn off
both gate drives.
The ADP3413 is specified over the commercial temperature
range of 0°C to 70°C and is available in an 8-lead SOIC package.
7V
D1
VCC
12V
ADP3413
BST
C
BST
IN
DRVH
Q1
SW
DELAY
+1V
DRVL
1V
PGND
OD
3
Q2
REV. A
Figure 1. General Application Circuit
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2002
ADP3413–SPECIFICATIONS
(T = 0 C to 70 C, VCC = 7 V, BST = 4 V to 26 V,
OD
> 2 V, unless otherwise noted.)
A
1
Parameter
SUPPLY
Supply Voltage Range
Quiescent Current
OD
INPUT
Input Voltage High
2
Input Voltage Low
2
Propagation Delay Time
PWM INPUT
Input Voltage High
2
Input Voltage Low
2
HIGH SIDE DRIVER
Output Resistance, Sourcing Current
Output Resistance, Sinking Current
Transition Times
3
(See Figure 2)
Propagation Delay
3, 4
(See Figure 2)
LOW SIDE DRIVER
Output Resistance, Sourcing Current
Output Resistance, Sinking Current
Transition Times
3
(See Figure 2)
Propagation Delay
3, 4
(See Figure 2)
Symbol
VCC
ICC
Q
Conditions
Min
4.15
Typ
Max
7.5
2
Unit
V
mA
V
V
ns
ns
V
V
Ω
Ω
Ω
Ω
ns
ns
ns
ns
Ω
Ω
Ω
Ω
ns
ns
ns
ns
1
2.0
tpdl
OD
tpdh
OD
2.3
15
15
0.8
30
30
0.8
V
BST
– V
SW
= 5 V
V
BST
– V
SW
= 7 V
V
BST
– V
SW
= 5 V
V
BST
– V
SW
= 7 V
V
BST
– V
SW
= 7 V, C
LOAD
= 3 nF
V
BST
– V
SW
= 7 V, C
LOAD
= 3 nF
V
BST
– V
SW
= 7 V
V
BST
– V
SW
= 7 V
VCC = 5 V
VCC = 7 V
VCC = 5 V
VCC = 7 V
VCC = 7 V, C
LOAD
= 3 nF
VCC = 7 V, C
LOAD
= 3 nF
VCC = 7 V
VCC = 7 V
3.0
2.0
1.25
1.0
36
20
65
22
3.0
2.0
1.5
1.0
27
19
30
17
5.0
3.5
2.5
2.5
47
30
86
32
5.0
3.5
3.0
2.5
35
26
35
25
tr
DRVH
tf
DRVH
tpdh
DRVH
tpdl
DRVH
tr
DRVL
tf
DRVL
tpdh
DRVL
tpdl
DRVL
NOTES
1
All limits at temperature extremes are guaranteed via correlation using standard Statistical Quality Control (SQC) methods.
2
Logic inputs meet typical CMOS I/O conditions for source/sink current (~1
µA).
3
AC specifications are guaranteed by characterization but not production tested.
4
For propagation delays, “tpdh” refers to the specified signal going high; “tpdl” refers to it going low.
Specifications subject to change without notice.
–2–
REV. A
ADP3413
ABSOLUTE MAXIMUM RATINGS*
ORDERING GUIDE
Model
Temperature Package
Range
Description
8-Lead Standard
Small Outline (SOIC)
Package
Option
SOIC-8
VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +8 V
BST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +30 V
BST to SW . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +8 V
SW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –5.0 V to +25 V
OD,
IN . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to VCC + 0.3 V
Operating Ambient Temperature Range . . . . . . . 0°C to 70°C
Operating Junction Temperature Range . . . . . . 0°C to 125°C
θ
JA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155°C/W
θ
JC
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40°C/W
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . . 300°C
*This
is a stress rating only; operation beyond these limits can cause the device to
be permanently damaged. Unless otherwise specified, all voltages are referenced
to PGND.
ADP3413JR 0°C to 70°C
PIN CONFIGURATION
BST
1
IN
2
8
DRVH
ADP3413
TOP VIEW
(Not To Scale)
7
SW
6
PGND
5
DRVL
OD
3
VCC
4
PIN FUNCTION DESCRIPTIONS
Pin
1
Mnemonic
BST
Function
Floating Bootstrap Supply for the Upper MOSFET. A capacitor connected between BST and SW Pins
holds this bootstrapped voltage for the high side MOSFET as it is switched. The capacitor should be
chosen between 100 nF and 1 F.
TTL-level input signal that has primary control of the drive outputs.
Output Disable. When low, this pin disables normal operation, forcing DRVH and DRVL low.
Input Supply. This pin should be bypassed to PGND with ~1
µF
ceramic capacitor.
Synchronous Rectifier Drive. Output drive for the lower (synchronous rectifier) MOSFET.
Power Ground. Should be closely connected to the source of the lower MOSFET.
This pin is connected to the buck-switching node, close to the upper MOSFET’s source. It is the floating
return for the upper MOSFET drive signal. It is also used to monitor the switched voltage to prevent turn-
on of the lower MOSFET until the voltage is below ~1 V. Thus, according to operating conditions, the
high low transition delay is determined at this pin.
Buck Drive. Output drive for the upper (buck) MOSFET.
2
3
4
5
6
7
IN
OD
VCC
DRVL
PGND
SW
8
DRVH
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the ADP3413 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. A
–3–
ADP3413
IN
tpdl
DRVL
tf
DRVL
tpdl
DRVH
tr
DRVL
DRVL
tf
DRVH
tpdh
DRVH
tr
DRVH
DRVH-SW
V
TH
V
TH
tpdh
DRVL
SW
1V
Figure 2. Nonoverlap Timing Diagram (Timing Is Referenced to the 90% and 10% Points Unless Otherwise Noted)
OD
tpdl
OD
DRVH
OR
DRVL
90%
tpdh
OD
10%
Figure 3. Output Disable Timing Diagram
–4–
REV. A
