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High Speed, Dual, 2 A MOSFET Driver
ADP3629/ADP3630/ADP3631
FEATURES
Industry-standard-compatible pinout
High current drive capability
Precise threshold shutdown comparator
UVLO with hysteresis
Overtemperature warning signal
Overtemperature shutdown
3.3 V-compatible inputs
Rise time and fall time: 10 ns typical at 2.2 nF load
Fast propagation delay
Matched propagation delays between channels
Supply voltage: 9.5 V to 18 V
Dual outputs can be operated in parallel
(ADP3629/ADP3630)
Rated from −40°C to +85°C ambient temperature
8-lead SOIC_N and 8-lead MSOP
GENERAL DESCRIPTION
The ADP3629/ADP3630/ADP3631 are dual, high current, high
speed drivers, capable of driving two independent N-channel
power MOSFETs. The ADP3629/ADP3630/ADP3631 use the
industry-standard footprint but add high speed switching per-
formance and improved system reliability.
The ADP3629/ADP3630/ADP3631 have an internal temperature
sensor and provide two levels of overtemperature protection: an
overtemperature warning and an overtemperature shutdown at
extreme junction temperatures.
The SD function, generated from a precise internal comparator,
provides fast system enable or shutdown. This feature allows
redundant overvoltage protection, complementing the protec-
tion inside the main controller device, or provides safe system
shutdown in the event of an overtemperature warning.
The wide input voltage range allows the driver to be compatible
with both analog and digital PWM controllers.
Digital power controllers are supplied from a low voltage supply,
and the driver is supplied from a higher voltage supply. The
ADP3629/ADP3630/ADP3631 add UVLO and hysteresis func-
tions, allowing safe startup and shutdown of the higher voltage
supply when used with low voltage digital controllers.
APPLICATIONS
AC-to-DC switch mode power supplies
DC-to-DC power supplies
Synchronous rectification
Motor drives
FUNCTIONAL BLOCK DIAGRAM
V
DD
ADP3629/ADP3630/ADP3631
8
SD
1
OVERTEMPERATURE
PROTECTION
V
EN
NONINVERTING
INA,
2
INA
INVERTING
PGND
3
UVLO
NONINVERTING
INB,
4
INB
INVERTING
V
DD
OTW
7
OUTA
6
VDD
5
OUTB
08401-101
Figure 1.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2009 Analog Devices, Inc. All rights reserved.
ADP3629/ADP3630/ADP3631
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Timing Diagrams.......................................................................... 4
Absolute Maximum Ratings............................................................ 6
Thermal Resistance ...................................................................... 6
ESD Caution .................................................................................. 6
Pin Configurations and Function Descriptions ........................... 7
Typical Performance Characteristics ............................................. 8
Test Circuit ...................................................................................... 10
Theory of Operation ...................................................................... 11
Input Drive Requirements (INA, INA, INB, INB, and SD) .. 11
Low-Side Drivers (OUTA, OUTB) .......................................... 11
Shutdown (SD) Function .......................................................... 11
Overtemperature Protections ................................................... 12
Supply Capacitor Selection ....................................................... 12
PCB Layout Considerations ...................................................... 12
Parallel Operation ...................................................................... 12
Thermal Considerations............................................................ 13
Outline Dimensions ....................................................................... 14
Ordering Guide .......................................................................... 14
REVISION HISTORY
9/09—Revision 0: Initial Version
Rev. 0 | Page 2 of 16
ADP3629/ADP3630/ADP3631
SPECIFICATIONS
V
DD
= 12 V, T
J
= −40°C to +125°C, unless otherwise noted.
1
Table 1.
Parameter
SUPPLY
Supply Voltage Range
Supply Current
Standby Current
UVLO
Turn-On Threshold Voltage
Turn-Off Threshold Voltage
Hysteresis
DIGITAL INPUTS (INA, INA, INB, INB, SD)
Input Voltage High
Input Voltage Low
Input Current
SD Threshold High
SD Threshold Low
SD Hysteresis
Internal Pull-Up/Pull-Down Current
OUTPUTS (OUTA, OUTB)
Output Resistance, Unbiased
Peak Source Current
Peak Sink Current
SWITCHING TIME
OUTA, OUTB Rise Time
OUTA, OUTB Fall Time
OUTA, OUTB Rising Propagation Delay
OUTA, OUTB Falling Propagation Delay
SD Propagation Delay Low
SD Propagation Delay High
Delay Matching Between Channels
OVERTEMPERATURE PROTECTION
Overtemperature Warning Threshold
Overtemperature Shutdown Threshold
Temperature Hysteresis for Shutdown
Temperature Hysteresis for Warning
Overtemperature Warning Low
1
Symbol
V
DD
I
DD
I
SBY
V
UVLO_ON
V
UVLO_OFF
Test Conditions/Comments
Min
9.5
Typ
Max
18
3
3
9.5
8.5
Unit
V
mA
mA
V
V
V
V
V
μA
V
V
V
mV
μA
kΩ
A
A
No switching, INA, INA, INB, and INB
disabled
SD = 5 V
V
DD
rising, T
A
= 25°C
V
DD
falling, T
A
= 25°C
8.0
7.0
1.2
1.2
8.7
7.7
1.0
V
IH
V
IL
I
IN
V
SD_H
V
SD_L
V
SD_HYST
2.0
0 V < V
IN
< V
DD
T
A
= 25°C
T
A
= 25°C
T
A
= 25°C
−20
1.19
1.21
0.95
240
0.8
+20
1.38
1.35
1.05
320
1.28
1.28
1.0
280
6
80
2
−2
10
10
14
22
32
48
2
VDD = PGND
See Figure 20
See Figure 20
t
RISE
t
FALL
t
D1
t
D2
t
dL_SD
t
dH_SD
C
LOAD
= 2.2 nF, see Figure 3 and Figure 4
C
LOAD
= 2.2 nF, see Figure 3 and Figure 4
C
LOAD
= 2.2 nF, see Figure 3 and Figure 4
C
LOAD
= 2.2 nF, see Figure 3 and Figure 4
See Figure 2
See Figure 2
25
25
30
35
45
75
ns
ns
ns
ns
ns
ns
ns
°C
°C
°C
°C
V
T
W
T
SD
T
HYS_SD
T
HYS_W
V
OTW_OL
See Figure 6
See Figure 6
See Figure 6
See Figure 6
Open drain, −500 μA
120
150
135
165
30
10
150
180
0.4
All limits at temperature extremes guaranteed via correlation using standard statistical quality control (SQC) methods.
Rev. 0 | Page 3 of 16
ADP3629/ADP3630/ADP3631
TIMING DIAGRAMS
SD
t
dL_SD
t
dH_SD
90%
10%
08401-002
OUTA,
OUTB
Figure 2. Shutdown Timing Diagram
INA,
INB
V
IH
V
IL
t
D1
t
RISE
t
D2
t
FALL
90%
OUTA,
OUTB
10%
90%
10%
08401-003
Figure 3. Output Timing Diagram (Noninverting)
INA,
INB
V
IL
V
IH
t
D1
t
RISE
t
D2
t
FALL
90%
OUTA,
OUTB
10%
90%
10%
08401-103
Figure 4. Output Timing Diagram (Inverting)
V
UVLO_ON
V
UVLO_OFF
V
DD
UVLO MODE
OUTPUTS DISABLED
NORMAL OPERATION
UVLO MODE
OUTPUTS DISABLED
Figure 5. UVLO Function
Rev. 0 | Page 4 of 16
08401-005
