a
FEATURES
1% Total Accuracy
630 A Typical Quiescent Current
Shutdown Current: 1 A (Typical)
Stable with 10 F Load Capacitor
4.5 V to 15 V Input Operating Range
Integrated Reverse Leakage Protection
6-Lead SOT-23-6 and 8-Lead SO-8 Packages
Programmable Charge Current
–20 C to +85 C Ambient Temperature Range
Internal Gate-to-Source Protective Clamp
APPLICATIONS
Li-Ion Battery Chargers
Desktop Computers
Hand-Held Instruments
Cellular Telephones
Battery Operated Devices
SD
Lithium-Ion
Battery Charger
ADP3820
FUNCTIONAL BLOCK DIAGRAM
BIAS
+
–
50mV
V
IN
IS
TE
V
REF
GATE
V
OUT
ADP3820
LE
V
IN
+5V
R
S
50m
C1
10 F
R1
10k
+
–
IS
V
IN
SD
GND
GENERAL DESCRIPTION
The ADP3820 is a precision single cell Li-Ion battery charge
controller that can be used with an external Power PMOS de-
vice to form a two-chip, low cost, low dropout linear battery
charger. It is available in two voltage options to accommodate
Li-Ion batteries with coke or graphite anodes. The ADP3820’s
high accuracy (± 1%) low shutdown current (1
µA)
and easy
charge current programming make this device especially attrac-
tive as a battery charge controller.
Charge current can be set by an external resistor. For example,
50 mΩ of resistance can be used to set the charge current to
1 A. Additional features of this device include foldback current
limit, overload recovery, and a gate-to-source voltage clamp to
protect the external MOSFET. The proprietary circuit also
minimizes the reverse leakage current from the battery if the
input voltage of the charger is disconnected. This feature elimi-
nates the need for an external serial blocking diode.
SO
NDP6020P
I
O
= 1A
V
OUT
Li-Ion
BATTERY
GATE
V
OUT
ADP3820-xx
GND
22 F
B
Figure 1. Li-Ion Charger Application Circuit
The ADP3820 operates with a wide input voltage range from
4.5 V to 15 V. It is specified over the industrial temperature
range of –20°C to +85°C and is available in the ultrasmall
6-lead surface mount SOT-23-6 and 8-lead SOIC packages.
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 1999
O
ADP3820–SPECIFICATIONS
1
(V
Parameter
INPUT VOLTAGE
OUTPUT VOLTAGE ACCURACY
QUIESCENT CURRENT
Shutdown Mode
Normal Mode
GATE TO SOURCE CLAMP VOLTAGE
GATE DRIVE MINIMUM VOLTAGE
2
GATE DRIVE CURRENT (SINK/SOURCE)
∆
V
GS
GAIN
∆
V
OUT
CURRENT LIMIT THRESHOLD VOLTAGE
LOAD REGULATION
LINE REGULATION
IN
= [V
OUT
+ 1 V] T
A
= –20 C to +85 C, unless otherwise noted)
Symbol
V
IN
Min
4.5
–1
Typ
Max
15
+1
Units
V
%
Conditions
V
IN
= V
OUT
+ 1 V to 15 V
V
SD
= 2 V
V
SD
= 0 V
V
SD
= 2 V
V
OUT
I
GND
I
GND
1
630
6
0.7
1
80
15
800
10
µA
µA
V
V
mA
dB
V
IN
– V
IS
I
OUT
= 10 mA to 1 A,
Circuit of Figure 1
TE
40
–10
–10
V
SD
2.0
I
SD
–15
3
I
DISCH
ORDERING GUIDE
75
+10
mV
mV
SD
INPUT VOLTAGE
SD
INPUT CURRENT
OUTPUT REVERSE LEAKAGE CURRENT
LE
Model
ADP3820ART-4.1
ADP3820ART-4.2
ADP3820AR-4.1
ADP3820AR-4.2
Voltage
Output
4.1 V
4.2 V
4.1 V
4.2 V
–2–
V
IN
= V
OUT
+ 1 V to 15 V
I
OUT
= 0.1 A
Circuit of Figure 1 (No Battery)
V
IH
V
IL
+10
0.4
+15
5
mV
V
V
µA
µA
V
SD
= 0 V to 5 V
V
IN
= Floating
ABSOLUTE MAXIMUM RATINGS*
O
Input Voltage, V
IN
. . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 V
Enable Input Voltage . . . . . . . . . . . . . . . 0.3 V to (V
IN
+ 0.3 V)
Operating Ambient Temperature Range . . . . –20°C to +85°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
θ
JA
, SO-8 Package . . . . . . . . . . . . . . . . . . . . . . . . 150°C/W
θ
JA
, SOT-23-6 Package . . . . . . . . . . . . . . . . . . . . 230°C/W
Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . +300°C
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . .+215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . .+220°C
ESD Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 kV
SO
NOTES
1
All limits at temperature extremes are guaranteed via correlation using standard Statistical Quality Control (SQC).
2
Provided gate-to-source clamp voltage is not exceeded.
Specifications subject to change without notice.
Package
Option*
Marking
Code
B
RT-6 (SOT-23-6) BAC
RT-6 (SOT-23-6) BBC
SO-8
SO-8
*SOT = Surface Mount Package. SO = Small Outline.
Contact the factory for availability of other output voltage options.
*This is a stress rating only; operation beyond these limits can cause the device
to be permanently damaged.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the ADP3820 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. A
ADP3820
PIN FUNCTION DESCRIPTIONS
PIN CONFIGURATIONS
SO-8
RT-6 (SOT-23-6)
8
SD
Pin
Pin
SOT-23-6 SO-8
1
2
8
7
Name
SD
GND
Function
Shutdown. Pulling this pin low
will disable the output.
Device Ground. This pin should
be tied to system ground closest
to the load.
Output Voltage Sense. This pin
is connected to the MOSFET’s
drain and directly to the load for
optimal load regulation. Bypass
to ground with a 10
µF
or larger
capacitor.
Gate drive for the external
MOSFET.
Input Voltage. This is also the
positive terminal connection of
the current sense resistor.
Current Sense. Used to sense the
input current by monitoring the
voltage across the current sense
resistor. It is connected to the
more negative terminal of the
resistor as well as the power
MOSFET’s source pin. IS pin
should be tied to the V
IN
pin if
the current limit feature is not
used.
No Connect.
IS
1
NC
2
SD
1
GND
2
6
IS
7
GND
TOP VIEW
GATE
3
(Not to Scale)
6
NC
ADP3820
5
V
IN
TOP VIEW
V
OUT 3
(Not to Scale)
4
GATE
ADP3820
V
IN 4
5
V
OUT
NC = NO CONNECT
3
5
V
OUT
4
5
3
4
GATE
V
IN
6
1
IS
2, 6
NC
REV. A
O
–3–
B
SO
LE
TE
ADP3820 –Typical Performance Characteristics
4.110
V
IN
= 5.1V
0.740
OUTPUT VOLTAGE – V
4.105
0.760
I
LOAD
= 10mA
0.720
I
GND
– mA
0.700
0.680
4.100
0.660
4.095
0.640
4.090
0
200
400
600
I
LOAD
– mA
800
1000
0.620
5
7
9
11
INPUT VOLTAGE – V
13
15
Figure 2. V
OUT
vs. I
LOAD
(V
IN
= 5.1 V)*
4.110
I
LOAD
= 1A
4.100
4.095
SO
11
13
15
I
GND
– mA
11
13
15
4.090
5
7
9
LE
I
GND
– mA
0.800
0.750
0.700
5
7
INPUT VOLTAGE – V
9
11
INPUT VOLTAGE – V
13
15
OUTPUT VOLTAGE – V
4.105
Figure 3. V
OUT
vs. V
IN
(I
LOAD
= 1 A)*
B
7
9
4.110
I
LOAD
= 10mA
OUTPUT VOLTAGE – V
4.105
O
4.100
4.095
4.090
5
TE
0.900
I
LOAD
= 1A
0.850
1.200
V
IN
= 5.1V
1.100
1.000
0.900
0.800
0.700
0.600
0.500
0.001
0.1
I
LOAD
– mA
10
Figure 5. I
GND
vs. V
IN
(I
LOAD
= 10 mA)*
Figure 6. I
GND
vs. V
IN
(I
LOAD
= 1 A)*
1000
INPUT VOLTAGE – V
Figure 4. V
OUT
vs. V
IN
(I
LOAD
= 10 mA)*
Figure 7. I
GND
vs. I
LOAD
(V
IN
= 5.1 V)*
*Reference
Figure 1.
–4–
REV. A
ADP3820
1.100
V
IN
= 5.1V
I
LOAD
= 10mA
1.000
4.190
0.900
OUTPUT VOLTAGE – V
4.230
4.210
V
OUT
= 4.2V
I
GND
– mA
4.170
4.150
4.130
V
OUT
= 4.1V
4.110
0.800
0.700
0.600
4.090
0.500
–40
4.070
–40
–20
0
20
40
TEMPERATURE – C
60
80
–20
0
20
40
TEMPERATURE – C
60
80
Figure 8. Quiescent Current vs. Temperature*
Figure 11. V
OUT
vs. Temperature, V
IN
= 5.1 V, I
LOAD
= 10 mA*
4.5
I
LOAD
= 10mA
4.0
3.5
OUTPUT VOLTAGE – V
3.0
2.5
2.0
1.5
1.0
0.5
0
0
1
2
SO
3
4
5
4
3
INPUT VOLTAGE – V
2
1
0
OUTPUT VOLTAGE – V
LE
–30
–40
–50
–60
–70
–80
–90
–100
10
100
1k
10k
100k
FREQUENCY – Hz
1M
10M
Figure 9. Power-Up/Power-Down*
PSRR – dB
INPUT
VOLTAGE – V
7.0
5.5
B
I
LOAD
= 10mA
C
OUT
= 10 F
O
OUTPUT
VOLTAGE – V
4.2
4.1
4.0
TE
0
–10
–20
C
LOAD
= 10 F
I
LOAD
= 1mA
5.000
V
IN
= 5.1V
R
S
= 0.5
4.000
3.000
2.000
1.000
0.000
0
20
40
60
80
I
LOAD
– mA
Figure 12. Ripple Rejection*
100
120
140
Figure 10. Line Transient Response (10
µ
F Output Cap)*
Figure 13. Current Limit Foldback*
REV. A
–5–
FPGA/CPLD
