Data Sheet
FEATURES
16-element FIFO for event recording
19 configurable I/Os allowing functions such as
Keypad decoding for matrix up to 11 × 8
Key press/release interrupts
Key pad lock/unlock
GPIO functions
GPI with selectable interrupt level
100 kΩ or 300 kΩ pull-up resistors
300 kΩ pull-down resistors
GPO with push-pull or open drain
Dual programmable logic blocks
PWM generator
Internal PWM generation
External PWM with internal PWM AND function
Clock divider
Reset generators
I
2
C interface with fast-mode plus (Fm+) support up to 1 MHz
Open-drain interrupt output
24-lead LFCSP 3.5 mm × 3.5 mm
25-ball WLCSP 1.99 mm × 1.99 mm
Keypad Decoder and I/O Expansion
ADP5589
FUNCTIONAL BLOCK DIAGRAM
VDD
GND
ADP5589
RST
SDA
SCL
INT
R0
R1
R2
R3
R4
R5
R6
R7
C0
C1
C2
C3
C4
C5
C6
PWM
RESET 1
GEN
09714-001
UVLO
POR
I
2
C INTERFACE
OSCILLATOR
KEY SCAN
AND
DECODE
GPI SCAN
AND
DECODE
REGISTERS
I/O
CONFIG
LOGIC 1
LOGIC 2
CLK DIV
APPLICATIONS
Devices requiring keypad entry and I/O expansion
capabilities
C7
C8
C9
C10
RESET 2
GEN
Figure 1.
GENERAL DESCRIPTION
The
ADP5589
is a 19 I/O port expander with built-in keypad
matrix decoder, programmable logic, reset generator, and
PWM generator. I/O expander ICs are used in portable devices
(phones, remote controls, and cameras) and nonportable
applications (healthcare, industrial, and instrumentation). I/O
expanders can be used to increase the number of I/Os available
to a processor or to reduce the number of I/Os required
through interface connectors for front panel designs.
The
ADP5589,
which handles all key scanning and decoding,
can flag the main processor via an interrupt line when new key
events have occurred. In addition, GPI changes and logic
changes can be tracked as events via the FIFO, eliminating the
need to monitor different registers for event changes. The
ADP5589
is equipped with a FIFO to store up to 16 events.
Events can be read back by the processor via an I
2
C compatible
interface.
The
ADP5589
frees up the main processor from having to
monitor the keypad, thereby reducing power consumption
and/or increasing processor bandwidth for performing other
functions.
The programmable logic functions allow common logic
requirements to be integrated as part of the GPIO expander,
saving board area and cost.
Rev. B
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ADP5589
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Absolute Maximum Ratings............................................................ 5
Thermal Resistance ...................................................................... 5
ESD Caution .................................................................................. 5
Pin Configuration and Function Descriptions ............................. 6
Quick Device Overview ................................................................... 7
Device Enable................................................................................ 8
Device Overview .......................................................................... 8
Detailed Description ........................................................................ 9
Data Sheet
Event FIFO .....................................................................................9
Key Scan Control ...........................................................................9
GPO Output ................................................................................ 15
Logic Blocks ................................................................................ 16
PWM Block ................................................................................. 17
Clock Divider Block ................................................................... 17
Reset Blocks ................................................................................ 17
Interrupts ..................................................................................... 18
Register Interface ............................................................................ 19
Register Map ................................................................................... 21
Detailed Register Descriptions ................................................. 23
Application Diagram...................................................................... 48
Outline Dimensions ....................................................................... 49
Ordering Guide .......................................................................... 49
REVISION HISTORY
1/13—Rev. A to Rev. B
Changes to Detailed Register Descriptions Section and
Table 7 .............................................................................................. 22
Changes to Table 33 and Table 34 ................................................ 29
Changes to Table 36 ........................................................................ 30
Changes to Table 37 ........................................................................ 31
Changes to Table 69 ........................................................................ 41
Changes to Table 84 ........................................................................ 46
Changes to Figure 31 ...................................................................... 48
8/11—Revision A: Initial Version
Rev. B | Page 2 of 52
Data Sheet
SPECIFICATIONS
VDD = 1.8 V to 3.3 V, T
A
= −40°C to +85⁰C, unless otherwise noted.
1
Table 1.
Parameter
SUPPLY VOLTAGE
VDD Input Voltage Range
Undervoltage Lockout Threshold
SUPPLY CURRENT
Standby Current
Operating Current (One Key Press)
Symbol
VDD
UVLO
VDD
Test Conditions/Comments
Min
1.65
1.2
Typ
ADP5589
Max
3.6
Unit
V
V
V
μA
µA
µA
µA
μA
μA
UVLO active, VDD falling
UVLO inactive, VDD rising
VDD = 1.65 V
VDD = 3.3 V
CORE_FREQ = 50 kHz, scan active,
300 kΩ pull-up, VDD = 1.65 V
CORE_FREQ = 50 kHz, scan active,
100 kΩ pull-up, VDD = 1.65 V
CORE_FREQ = 50 kHz, scan active,
300 kΩ pull-up, VDD = 3.3 V
CORE_FREQ = 50 kHz, scan active,
100 kΩ pull-up, VDD = 3.3 V
1.3
1.4
1
1
30
35
75
80
1.6
4
10
40
45
85
90
I
STNBY
I
SCAN = 10 ms
I
SCAN = 10 ms
I
SCAN = 10 ms
I
SCAN = 10 ms
PULL-UP, PULL-DOWN RESISTANCE
Pull-Up Option 1
Pull-Up Option 2
Pull-Down
INPUT LOGIC LEVEL (RST, SCL, SDA, R0, R1, R2, R3, R4,
R5, R6, R7, C0, C1, C2, C3, C4, C5, C6, C7, C8, C9, C10)
Logic Low Input Voltage
Logic High Input Voltage
Input Leakage Current (Per Pin)
PUSH-PULL OUTPUT LOGIC LEVEL (R0, R1, R2, R3, R4,
R5, R6, R7, C0, C1, C2, C3, C4, C5, C6, C7, C8, C9, C10)
Logic Low Output Voltage
2
Logic Low Output Voltage
3
Logic High Output Voltage
Logic High Leakage Current (Per Pin)
OPEN-DRAIN OUTPUT LOGIC LEVEL (INT, SDA)
Logic Low Output Voltage (INT)
Logic Low Output Voltage (SDA)
Logic High Leakage Current (Per Pin)
Logic Propagation Delay
FF1 Hold Time
4
FF1 Setup Time
4
FF2 Hold Time
4
FF2 Setup Time
4
GPIO Debounce
4
Internal Oscillator Frequency
5
I
2
C TIMING SPECIFICATIONS
Delay from UVLO/Reset Inactive to I
2
C Access
SCL Clock Frequency
SCL High Time
SCL Low Time
Data Setup Time
Data Hold Time
Setup Time for Repeated Start
50
150
150
100
300
300
150
450
450
kΩ
kΩ
kΩ
V
IL
V
IH
V
I-Leak
0.7 × VDD
0.1
0.3 × VDD V
V
1
µA
V
OL
V
OL
V
OH
V
OH-Leak
V
OL
V
OL
V
OH-Leak
Sink current = 10 mA
Sink current = 10 mA
Source current = 5 mA
0.4
0.5
0.7 × VDD
0.1
1
0.4
0.4
1
300
V
V
V
µA
V
V
µA
ns
ns
ns
ns
ns
µs
kHz
µs
kHz
µs
µs
ns
µs
µs
I
SINK
= 10 mA
I
SINK
= 20 mA
0.1
125
0
175
0
175
900
1000
OSC
FREQ
70
1100
60
1000
f
SCL
t
HIGH
t
LOW
t
SU; DAT
t
HD; DAT
t
SU; STA
0
0.26
0.5
50
0
0.26
Rev. B | Page 3 of 52
ADP5589
Parameter
Hold Time for Start/Repeated Start
Bus Free Time for Stop and Start Condition
Setup Time for Stop Condition
Data Valid Time
Data Valid Acknowledge
Rise Time for SCL and SDA
Fall Time for SCL and SDA
Pulse Width of Suppressed Spike
Capacitive Load for Each Bus Line
1
2
Data Sheet
Symbol
t
HD; STA
t
BUF
t
SU; STO
t
VD; DAT
t
VD; ACK
t
R
t
F
t
SP
C
B 6
Test Conditions/Comments
Min
0.26
0.5
0.26
Typ
Max
Unit
µs
µs
µs
µs
µs
ns
ns
ns
pF
0
0.45
0.45
120
120
50
550
All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC). Typical values are at T
A
= 25°C, VDD = 1.8 V.
Maximum of five GPIOs active simultaneously.
3
All GPIOs active simultaneously.
4
Guaranteed by design.
5
All timers are referenced from the base oscillator and have the same ±10% accuracy.
6
C
B
is the total capacitance of one bus line in picofarads.
t
F
SDA
70%
30%
t
R
70%
30%
t
SU; DAT
t
F
70%
30%
t
HD; DAT
t
R
70%
30%
70%
30%
t
VD; DAT
t
HIGH
70%
30%
SCL
t
HD; STA
S
1/
f
SCL
FIRST CLOCK CYCLE
t
LOW
NINTH CLOCK
t
BUF
SDA
t
SU; STA
t
HD; STA
t
SP
70%
30%
t
VD; ACK
t
SU; STO
SCL
Sr
V
IL
= 0.3VDD
V
IH
= 0.7VDD
P
NINTH CLOCK
S
09714-002
Figure 2. I
2
C Interface Timing Diagram
Rev. B | Page 4 of 52
