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ADS5413
SLWS153 − DECEMBER 2003
SINGLE 12-BIT, 65-MSPS IF SAMPLING
ANALOG-TO-DIGITAL CONVERTER
FEATURES
D
D
D
D
D
D
D
D
D
12-Bit Resolution
65-MSPS Maximum Sample Rate
2-Vpp Differential Input Range
3.3-V Single Supply Operation
1.8-V to 3.3-V Output Supply
400-mW Total Power Dissipation
Two’s Complement Output Format
On-Chip S/H and Duty Cycle Adjust Circuit
Internal or External Reference
D
48-Pin TQFP Package With PowerPad
(7 mm x 7 mm body size)
D
64.5-dBFS SNR and 72-dBc SFDR at 65 MSPS
and 190-MHz Input
D
Power-Down Mode
D
Single-Ended or Differential Clock
D
1-GHz −3-dB Input Bandwidth
APPLICATIONS
D
High IF Sampling Receivers
D
Medical Imaging
D
Portable Instrumentation
DESCRIPTION
The ADS5413 is a low power, 12-bit, 65-MSPS, CMOS pipeline analog-to-digital converter (ADC) that operates from a
single 3.3-V supply, while offering the choice of digital output levels from 1.8 V to 3.3 V. The low noise, high linearity, and
low clock jitter makes the ADC well suited for high-input frequency sampling applications. On-chip duty cycle adjust circuit
allows the use of a non-50% duty cycle. This can be bypassed for applications requiring low jitter or asynchronous
sampling. The device can also be clocked with single ended or differential clock, without change in performance. The
internal reference can be bypassed to use an external reference to suit the accuracy and low drift requirements of the
application.
The device is specified over full temperature range (−40°C to +85°C).
FUNCTIONAL BLOCK DIAGRAM
AVDD
OVDD
PWD
S/H
VINP
VINN
REF SEL
VREFT
CML
VREFB
VBG
CLK
DCA
CLKC
DCA
D[0:11]
AGND
OGND
2.25 V
A/D
D/A
A/D
D/A
Σ
Gain
Stage
Σ
7 Stages
A/D
D/A
Gain
Stage
Σ
Gain
Stage
Flash
A/D
Internal
Reference
1.25 V Generator
1.8 V
2
2
2
2
Digital Error Correction
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
CommsADC is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date. Products
conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters.
Copyright
2003, Texas Instruments Incorporated
ADS5413
SLWS153 − DECEMBER 2003
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during
storage or handling to prevent electrostatic damage to the MOS gates.
PACKAGE/ORDERING INFORMATION
(1)
PRODUCT
PACKAGE LEAD
HTQFP-48
(2)
PowerPAD
PACKAGE
DESIGNATOR
PHP
SPECIFIED
TEMPERATURE
RANGE
−40°C to 85°C
PACKAGE
MARKING
AZ5413
ORDERING
NUMBER
ADS5413IPHP
TRANSPORT
MEDIA, QUANTITY
Tray, 250
ADS5413
(1)
(2)
For the most current product and ordering information, see the Package Option Addendum located at the end of this data sheet.
Thermal pad size: 3,5 mm
×
3,5 mm
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted
(1)
UNITS
AVDD measured with respect to AGND
Supply voltage range
OVDD measure with respect to OGND
Digital input, measured with respect to AGND
Reference inputs Vrefb or Vreft, measured with respect to AGND
Analog inputs Vinp or Vinn, measured with respect to AGND
Maximum storage temperature
Soldering reflow temperature
(1)
−0.3 V to 3.9 V
−0.3 V to 3.9 V
−0.3 V to AVDD + 0.3 V
−0.3 V to AVDD + 0.3 V
−0.3 V to AVDD + 0.3 V
150°C
235°C
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
(1)
MIN
ENVIRONMENTAL
Operating free-air temperature, T
A
SUPPLIES
Analog supply voltage, V
(AVDD)
Output driver supply voltage, V
(OVDD)
ANALOG INPUTS
Input common-mode voltage
Differential input voltage range
CLOCK INPUTS, CLK AND CLKC
Sample rate, f
S
= 1/t
c
Differential input swing (see Figure 17)
Differential input common-mode voltage (see Figure 18)
Clock pulse width high, t
w(H)
(see Figure 16, with DCA off)
Clock pulse width low, t
w(L)
(see Figure 16, with DCA off)
(1)
(2)
NOM
MAX
85
UNIT
°C
V
V
V
V
PP
−40
3
1.6
CML
(2)
2
5
1
1.65
6.92
6.92
3.3
3.6
3.6
65
6
MHz
V
PP
V
ns
ns
Recommended by design and characterization but not tested at final production unless specified under the
electrical characteristics
section.
See V
(CML)
in the internal reference generator section.
2
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ADS5413
SLWS153 − DECEMBER 2003
ELECTRICAL CHARACTERISTICS
over operating free-air temperature range, clock frequency = 65 MSPS, 50% clock duty cycle (AVDD = OVDD = 3.3 V), duty cylce adjust off,
internal reference, A
IN
= −1 dBFS, 1.2-V
PP
square differential clock (unless otherwise noted)
PARAMETER
DC PERFORMANCE
Power Supply
Total analog supply current with internal
reference and DCA on
I
(AVDD)
Analog supply current with external reference
and DCA on
Analog supply current with internal and DCA off
reference
I
(OVDD)
P
D
P
D
Digital output driver supply current
Total power dissipation
Power down dissipation
No missing codes
DNL
INL
E
O
E
G
V
REFB
V
REFT
Differential nonlinearity
Integral nonlinearity
Offset error
Gain error
Reference bottom
Reference top
V
REFT
− V
REFB
V
REFT
− V
REFB
variation (6σ)
V
(CML)
I
IH
I
IL
V
IH
V
IL
V
OH
V
OL
Common-mode output voltage
High-level input current
Low-level input current
High-level input voltage
Low-level input voltage
High-level output voltage
Low-level output voltage
I
OH
= 50
µA
I
OL
= −50
µA
f
IN
= 14 MHz
f
IN
= 39 MHz
SNR
Signal-to-noise ratio
f
IN
= 70 MHz
f
IN
= 150 MHz
f
IN
= 220 MHz
f
IN
= 14 MHz
f
IN
= 39 MHz
SINAD
Signal-to-noise and distortion
f
IN
= 70 MHz
f
IN
= 150 MHz
f
IN
= 220 MHz
f
IN
= 14 MHz
f
IN
= 39 MHz
SFDR
Spurious free dynamic range
f
IN
= 70 MHz
f
IN
= 150 MHz
f
IN
= 220 MHz
72
62.5
63
68.5
68.5
68.2
64.8
63.8
67.6
67.8
67.9
63.2
63
77.5
79
81
69
72
dBc
dBFS
dBFS
2.4
0.8
V
I
= 2.4 V
V
I
= 0.3 V
−60
−60
2
0.8
Digital Inputs (PWD, DCA, REF SEL)
60
60
µA
µA
V
V
V
V
Sinewave input, f
IN
= 2 MHz
Sinewave input, f
IN
= 2 MHz
Sinewave input, f
IN
= 2 MHz
Sinewave input, f
IN
= 2 MHz
1.1
2.1
−0.9
−2
A
IN
= 0 dBFS, f
IN
= 2 MHz
A
IN
= 0 dBFS, f
IN
= 2 MHz
PWDN = high
A
IN
= 0 dBFS, f
IN
= 2 MHz
113
96
107
8
400
23
Assured
±0.5
±1
3
0.3
1.25
2.25
1.06
0.06
1.8
1.4
2.4
1
2
LSB
LSB
mV
%FS
V
V
V
V
V
480
50
mA
mW
mW
mA
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DC Accuracy
Internal Reference Generator
Digital Outputs
AC PERFORMANCE
3
ADS5413
SLWS153 − DECEMBER 2003
www.ti.com
ELECTRICAL CHARACTERISTICS (CONTINUED)
over operating free-air temperature range, clock frequency = 65 MSPS, 50% clock duty cycle (AVDD = OVDD = 3.3 V), duty cylce adjust off,
internal reference, A
IN
= −1 dBFS, 1.2-V
PP
square differential clock (unless otherwise noted)
PARAMETER
AC PERFORMANCE (Continued)
f
IN
= 14 MHz
f
IN
= 39 MHz
HD2
Second order harmonic
f
IN
= 70 MHz
f
IN
= 150 MHz
f
IN
= 220 MHz
f
IN
= 14 MHz
f
IN
= 39 MHz
HD3
Third order harmonic
f
IN
= 70 MHz
f
IN
= 150 MHz
f
IN
= 220 MHz
Two tone IMD rejection, A
1,2
= −7 dBFS
Analog input bandwidth
f
1
= 220 MHz,
f
2
= 225 MHz
−3 dB BW respect to −3 dBFS input at low
frequency
90
90
90
83
72
77.5
79
81
69
77
69
1
dBc
GHz
dBc
dBc
TEST CONDITIONS
MIN
TYP
MAX
UNIT
TIMING CHARACTERISTICS
25°C, C
L
= 10 pF
MIN
Aperture delay
t
d(A)
t
d(Pipe)
t
d1
t
d2
t
d1
t
d2
t
d1
t
d2
t
d1
t
d2
(1)
TYP
2
0.4
6
8
MAX
UNIT
ns
ps
Cycles
ns
ns
ns
ns
Aperture jitter
Latency
Propagation delay from clock input to beginning of data stable
(1)
Propagation delay from clock input to end of data stable
(1)
Propagation delay from clock input to beginning of data stable
(1)
Propagation delay from clock input to end of data stable
(1)
Propagation delay from clock input to beginning of data stable
(1)
Propagation delay from clock input to end of data
stable
(1)
DCS on, OVDD = 1.8 V
DCS on, OVDD = 3.3 V
Propagation delay from clock input to beginning of data stable
(1)
Propagation delay from clock input to end of data stable
(1)
DCS off, OVDD = 3.3 V
DCS off, OVDD = 1.8 V
20.3
7
20.3
10
22.3
9
22.3
Data stable if V
O
< 10% OVDD or V
O
> 90% OVDD
TIMING DIAGRAM
Sample N
VINP
t
d(A)
t
w(H)
t
w(L)
t
d(Pipe)
CLK
t
c
t
d2(O)
Data N−6
Data N−5
Data N−4
Data N−3
Data N−2
Data N−1
Data N
Data N+1
Data N+2
D[0:11]
Data N−7
t
d1(O)
Figure 1. ADS5413 Timing Diagram
4
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ADS5413
SLWS153 − DECEMBER 2003
PIN ASSIGNMENTS
PHP PACKAGE
(TOP VIEW)
REF SEL
AVDD
OGND
AVDD
AGND
AGND
AGND
AGND
OVDD
NC
AVDD
AVDD
48 47 46 45 44 43 42 41 40 39 38 37
AVDD
AGND
VINP
VINN
AGND
CML
AVDD
VREFB
VREFT
AVDD
AGND
NC
1
2
3
4
5
6
7
8
9
10
11
12
13 14 15 16 17 18 19 20 21 22 23 24
THERMAL PAD
(Connect to GND Plane)
36
35
34
33
32
31
30
29
28
27
26
25
D0 (LSB)
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11 (MSB)
NC
DECOUPLING
PWD
NC
CLK
CLKC
VBG
Terminal Functions
TERMINAL
NAME
AVDD
AGND
CLK
CLKC
CML
D11−D0
DCA
DECOUPLING
NC
OGND
OVDD
PWD
REF SEL
VBG
VINN
VINP
VREFB
VREFT
NO.
1, 7, 10, 18,
40, 44, 45, 47
2, 5, 11, 21,
41, 42, 43, 46
19
20
6
25−36
24
15
12, 14, 17, 37
22, 39
23, 38
16
48
13
4
3
8
9
I
I
I
I
O
I
I
I/O
I/O
I/O
I
I
I
I
O
O
I
O
Analog power supply
Analog ground
Clock input
Complementary clock input
Common-mode output voltage
Digital outputs, D11 is most significant data bit, D0 is least significant data bit.
Duty cycle adjust control. High = enable, low = disable, NC = enable
Decoupling pin. Add 0.1
µF
to GND
Internally not connected
Digital driver ground
Digital driver power supply
Power down. High = powered down, low = powered up, NC = powered up
Reference select. High = external reference, low = internal reference, NC = internal reference
Bandgap voltage output
Complementary analog input
Analog input
Reference bottom
Reference top
5
DESCRIPTION
AGND
OGND
OVDD
DCA
AVDD
stm32/stm8
