a
SUMMARY
High performance signal processor for communications,
graphics, and imaging applications
Super Harvard Architecture
Four independent buses for dual data fetch, instruction
fetch, and nonintrusive I/O
32-bit IEEE floating-point computation units—multiplier,
ALU, and shifter
Dual-ported on-chip SRAM and integrated I/O peripherals—a
complete system-on-a-chip
Integrated multiprocessing features
Commercial Grade
SHARC DSP Microcomputer
ADSP-21061/ADSP-21061L
Dual data address generators with modulo and bit-reverse
addressing
Efficient program sequencing with zero-overhead looping:
single-cycle loop setup
IEEE JTAG Standard 1149.1 test access port and on-chip
emulation
32-bit single-precision and 40-bit extended-precision IEEE
floating-point data formats or 32-bit fixed-point data
format
240-lead MQFP package, thermally enhanced MQFP, 225-ball
plastic ball grid array (PBGA)
Lead (Pb) free packages.
For more information, see Ordering
Guide on Page 52.
KEY FEATURES—PROCESSOR CORE
50 MIPS, 20 ns instruction rate, single-cycle instruction
execution
120 MFLOPS peak, 80 MFLOPS sustained performance
CORE PROCESSOR
TIMER
INSTRUCTION
CACHE
32 48-BIT
DUAL-PORTED SRAM
B LOCK 0
TWO INDEPENDENT
DUAL-PORTED BLOCKS
JTAG
BLOCK 1
TEST AND
EMULATION
7
8
DAG1
4 32
8
DAG2
4 24
PROCESSOR PORT
I/O PORT
ADDR
DATA
ADDR
DATA
DATA
ADDR
ADDR
DATA
PROGRAM
SEQUENCER
24
32
IOD
48
IOA
17
EXTERNAL
PORT
32
PM ADDRESS BUS
DM ADDRESS BUS
ADDR BUS
MUX
MULTIPROCESSOR
INTERFACE
PM DATA BUS
BUS
CONNECT
(PX)
DM DATA BUS
48
40/32
DATA BUS
MUX
48
S
DATA
REGISTER
FILE
MULT
16
40-BIT
BARREL
SHIFTER
ALU
IOP
REGISTERS
(MEMORY
MAPPED)
CONTROL,
STATUS AND
DATA BUFFERS
DMA
CONTROLLER
SERIAL PORTS
(2)
HOST PORT
4
6
6
I/O PROCESSOR
Figure 1. Functional Block Diagram
SHARC and the SHARC logo are registered trademarks of Analog Devices, Inc.
Rev. D
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ADSP-21061/ADSP-21061L
TABLE OF CONTENTS
Summary ............................................................... 1
Key Features—Processor Core ................................. 1
General Description ................................................. 3
SHARC Family Core Architecture ............................ 3
Memory and I/O Interface Features ........................... 4
Porting Code From the ADSP-21060 or
ADSP-21062 ..................................................... 7
Development Tools ............................................... 7
Additional Information .......................................... 8
Related Signal Chains ............................................ 8
Pin Function Descriptions ......................................... 9
Target Board Connector For EZ-ICE Probe ............... 12
ADSP-21061 Specifications ...................................... 14
Operating Conditions (5 V) ................................... 14
Electrical Characteristics (5 V) ............................... 14
Internal Power Dissipation (5 V) ............................ 15
External Power Dissipation (5 V) ............................ 16
ADSP-21061L Specifications ..................................... 17
Operating Conditions (3.3 V) ................................. 17
Electrical Characteristics (3.3 V) ............................. 17
Internal Power Dissipation (3.3 V) .......................... 18
External Power Dissipation (3.3 V) .......................... 19
Absolute Maximum Ratings ................................... 20
ESD Caution ...................................................... 20
Package Marking Information ................................ 20
Timing Specifications ........................................... 20
Test Conditions .................................................. 43
Environmental Conditions .................................... 46
225-Ball PBGA Pin Configurations ............................. 47
240-Lead MQFP Pin Configurations ........................... 49
Outline Dimensions ................................................ 50
Surface-Mount Design .......................................... 52
Ordering Guide ..................................................... 52
REVISION HISTORY
5/13—Rev C to Rev D
Updated
Development Tools .......................................7
Added
Related Signal Chains .......................................8
Removed the ADSP-21061LAS-176, ADSP-21061LKS-160, and
ADSP-21061LKS-176 models from
Ordering Guide ........ 52
GENERAL NOTE
This data sheet represents production released specifications for
the ADSP-21061 (5 V) and ADSP-21061L (3.3 V) processors for
33 MHz, 40 MHz, 44 MHz, and 50 MHz speed grades. The
product name“ADSP-21061” is used throughout this data sheet
to represent all devices, except where expressly noted.
Rev. D | Page 2 of 52 | May 2013
ADSP-21061/ADSP-21061L
GENERAL DESCRIPTION
The ADSP-21061 SHARC—Super Harvard Architecture Com-
puter—is a signal processing microcomputer that offers new
capabilities and levels of performance. The ADSP-21061
SHARC is a 32-bit processor optimized for high performance
DSP applications. The ADSP-21061 builds on the ADSP-21000
DSP core to form a complete system-on-a-chip, adding a dual-
ported on-chip SRAM and integrated I/O peripherals supported
by a dedicated I/O bus.
Fabricated in a high speed, low power CMOS process, the
ADSP-21061 has a 20 ns instruction cycle time and operates at
50 MIPS. With its on-chip instruction cache, the processor can
execute every instruction in a single cycle.
Table 1
shows perfor-
mance benchmarks for the ADSP-21061/ADSP-21061L.
The ADSP-21061 SHARC represents a new standard of integra-
tion for signal computers, combining a high performance
floating-point DSP core with integrated, on-chip system fea-
tures including 1M bit SRAM memory, a host processor
interface, a DMA controller, serial ports, and parallel bus con-
nectivity for glueless DSP multiprocessing.
Table 1. Benchmarks (at 50 MHz)
Benchmark Algorithm
1024 Point Complex FFT (Radix 4,
with reversal)
FIR Filter (per tap)
IIR Filter (per biquad)
Divide (y/x)
Inverse Square Root
DMA Transfer Rate
Speed
.37 ms
20 ns
80 ns
120 ns
180 ns
300M bps
Cycles
18,221
1
4
6
9
• Serial ports
• JTAG test access port
ADSP-21061
1
CLOCK
TO GND
CLKIN
EBOOT
3
4
LBOOT
IRQ
2–0
FLAG
3–0
TIMEXP
ADDR
31–0
DATA
47–0
RD
TCLK0
RCLK0
TFS0
RSF0
DT0
DR0
WR
ACK
MS
3–0
CONTROL
BMS
CS
ADDR
DATA
ADDR
BOOT
EPROM
(OPTIONAL)
PAGE
SW
SBTS
ADRCLK
DMAR
1–2
DMAG
1–2
CS
HBR
HBG
REDY
BR
1–6
CPA
JTAG
7
ADDRESS
DATA
SERIAL
DEVICE
(OPTIONAL)
DATA MEMORY-
MAPPED
OE
DEVICES
WE
(OPTIONAL)
ACK
CS
DMA DEVICE
(OPTIONAL)
DATA
SERIAL
DEVICE
(OPTIONAL)
TCLK1
RCLK1
TFS1
RSF1
DT1
DR1
HOST
PROCESSOR
INTERFACE
(OPTIONAL)
ADDR
DATA
RPBA
ID
2–0
RESET
Figure 2. ADSP-21061/ADSP-21061L System Sample Configuration
SHARC FAMILY CORE ARCHITECTURE
The ADSP-21061 includes the following architectural features
of the ADSP-21000 family core. The ADSP-21061 processors
are code- and function-compatible with the ADSP-21020,
ADSP-21060, and ADSP-21062 SHARC processors.
The ADSP-21061 continues SHARC’s industry-leading stan-
dards of integration for DSPs, combining a high performance
32-bit DSP core with integrated, on-chip system features.
The block diagram
on Page 1,
illustrates the following architec-
tural features:
• Computation units (ALU, multiplier, and shifter) with a
shared data register file
• Data address generators (DAG1, DAG2)
• Program sequencer with instruction cache
• PM and DM buses capable of supporting four 32-bit data
transfers between memory and the core at every core pro-
cessor cycle
• Interval timer
• On-chip SRAM
• External port for interfacing to off-chip memory and
peripherals
• Host port and multiprocessor interface
• DMA controller
Independent, Parallel Computation Units
The arithmetic/logic unit (ALU), multiplier, and shifter all per-
form single-cycle instructions. The three units are arranged in
parallel, maximizing computational throughput. Single multi-
function instructions execute parallel ALU and multiplier oper-
ations. These computation units support IEEE 32-bit single-
precision floating-point, extended-precision 40-bit floating-
point, and 32-bit fixed-point data formats.
Data Register File
A general-purpose data register file is used for transferring data
between the computation units and the data buses, and for stor-
ing intermediate results. This 10-port, 32-register (16 primary,
16 secondary) register file, combined with the ADSP-21000
Harvard architecture, allows unconstrained data flow between
computation units and internal memory.
Rev. D | Page 3 of 52 | May 2013
ADSP-21061/ADSP-21061L
Single-Cycle Fetch of Instruction and Two Operands
The ADSP-21061 features an enhanced Harvard architecture in
which the data memory (DM) bus transfers data and the pro-
gram memory (PM) bus transfers both instructions and data
(Figure
1 on Page 1).
With its separate program and data mem-
ory buses and on-chip instruction cache, the processor can
simultaneously fetch two operands and an instruction (from the
cache), all in a single cycle.
A 16-bit floating-point storage format is supported, which effec-
tively doubles the amount of data that may be stored on-chip.
Conversion between the 32-bit floating-point and 16-bit float-
ing-point formats is done in a single instruction.
While each memory block can store combinations of code and
data, accesses are most efficient when one block stores data,
using the DM bus for transfers, and the other block stores
instructions and data, using the PM bus for transfers. Using the
DM bus and PM bus in this way, with one dedicated to each
memory block, assures single-cycle execution with two data
transfers. In this case, the instruction must be available in the
cache. Single-cycle execution is also maintained when one of the
data operands is transferred to or from off-chip, via the
ADSP-21061’s external port.
Instruction Cache
The ADSP-21061 includes an on-chip instruction cache that
enables three-bus operation for fetching an instruction and two
data values. The cache is selective—only the instructions whose
fetches conflict with PM bus data accesses are cached. This
allows full-speed execution of core, looped operations such as
digital filter multiply-accumulates and FFT butterfly processing.
Off-Chip Memory and Peripherals Interface
The ADSP-21061’s external port provides the processor’s inter-
face to off-chip memory and peripherals. The 4-gigaword off-
chip address space is included in the ADSP-21061’s unified
address space. The separate on-chip buses—for program mem-
ory, data memory, and I/O—are multiplexed at the external port
to create an external system bus with a single 32-bit address bus
and a single 48-bit (or 32-bit) data bus. The on-chip Super Har-
vard Architecture provides three-bus performance, while the
off-chip unified address space gives flexibility to the designer.
Addressing of external memory devices is facilitated by on-chip
decoding of high order address lines to generate memory bank
select signals. Separate control lines are also generated for sim-
plified addressing of page-mode DRAM. The ADSP-21061
provides programmable memory wait states and external mem-
ory acknowledge controls to allow interfacing to DRAM and
peripherals with variable access, hold, and disable time
requirements.
Data Address Generators with Hardware Circular Buffers
The ADSP-21061’s two data address generators (DAGs) imple-
ment circular data buffers in hardware. Circular buffers allow
efficient programming of delay lines and other data structures
required in digital signal processing, and are commonly used in
digital filters and Fourier transforms. The two DAGs of the
ADSP-21061 contain sufficient registers to allow the creation of
up to 32 circular buffers (16 primary register sets, 16 secondary).
The DAGs automatically handle address pointer wraparound,
reducing overhead, increasing performance and simplifying
implementation. Circular buffers can start and end at any mem-
ory location.
Flexible Instruction Set
The 48-bit instruction word accommodates a variety of parallel
operations, for concise programming. For example, the
ADSP-21061 can conditionally execute a multiply, an add, a
subtract, and a branch, all in a single instruction.
Host Processor Interface
The ADSP-21061’s host interface allows easy connection to
standard microprocessor buses, both 16-bit and 32-bit, with lit-
tle additional hardware required. Asynchronous transfers at
speeds up to the full clock rate of the processor are supported.
The host interface is accessed through the ADSP-21061’s exter-
nal port and is memory-mapped into the unified address space.
Two channels of DMA are available for the host interface; code
and data transfers are accomplished with low software
overhead.
The host processor requests the ADSP-21061’s external bus
with the host bus request (HBR), host bus grant (HBG), and
ready (REDY) signals. The host can directly read and write the
internal memory of the ADSP-21061, and can access the DMA
channel setup and mailbox registers. Vector interrupt support is
provided for efficient execution of host commands.
MEMORY AND I/O INTERFACE FEATURES
The ADSP-21061 processors add the following architectural
features to the SHARC family core.
Dual-Ported On-Chip Memory
The ADSP-21061 contains one megabit of on-chip SRAM, orga-
nized as two blocks of 0.5M bits each. Each bank has eight 16-bit
columns with 4k 16-bit words per column. Each memory block
is dual-ported for single-cycle, independent accesses by the core
processor and I/O processor or DMA controller. The dual-
ported memory and separate on-chip buses allow two data
transfers from the core and one from I/O, all in a single cycle
(see
Figure 4
for the ADSP-21061 memory map).
On the ADSP-21061, the memory can be configured as a maxi-
mum of 32k words of 32-bit data, 64k words for 16-bit data, 16k
words of 48-bit instructions (and 40-bit data) or combinations
of different word sizes up to 1 megabit. All the memory can be
accessed as 16-bit, 32-bit, or 48-bit.
DMA Controller
The ADSP-21061’s on-chip DMA controller allows zero-
overhead data transfers without processor intervention. The
DMA controller operates independently and invisibly to the
processor core, allowing DMA operations to occur while the
core is simultaneously executing its program instructions.
Rev. D | Page 4 of 52 | May 2013
ADSP-21061/ADSP-21061L
CONTROL
ADDRESS
ADDRESS
ADSP-21061 #6
ADSP-21061 #5
ADSP-21061 #4
ADSP-21061 #3
CLKIN
RESET
RPBA
3
ID2–0
011
CONTROL
ADDR31–0
DATA47–0
BR1–2, BR4–6
BR3
5
ADSP-21061 #2
CLKIN
RESET
RPBA
3
ID2–0
CONTROL
010
ADDR31–0
DATA47–0
CPA
BR1, BR3–6
BR2
5
CONTROL
ADSP-21061 #1
CLKIN
RESET
RPBA
3
ID2–0
ADDR31–0
DATA47–0
RDx
CONTROL
DATA
DATA
ADDR
DATA
OE
WE
ACK
CS
CS
ADDR
DATA
GLOBAL MEMORY
AND
PERIPHERAL (OPTIONAL)
WRx
ACK
MS3–0
BMS
PAGE
SBTS
001
BOOT EPROM (OPTIONAL)
BUS
PRIORITY
RESET
CLOCK
CS
HBR
HBG
REDY
CPA
BR2–6
BR1
ADDR
5
DATA
HOST PROCESSOR
INTERFACE (OPTIONAL)
Figure 3. Shared Memory Multiprocessing System
DMA transfers can occur between the ADSP-21061’s internal
memory and either external memory, external peripherals, or a
host processor. DMA transfers can also occur between the
ADSP-21061’s internal memory and its serial ports.
DMA transfers between external memory and external periph-
eral devices are another option. External bus packing to 16-,
32-, or 48-bit words is performed during DMA transfers.
Rev. D | Page 5 of 52 | May 2013
