a
SUMMARY
16-Bit Fixed-Point DSP Microprocessors with
On-Chip Memory
Enhanced Harvard Architecture for Three-Bus
Performance: Instruction Bus and Dual Data Buses
Independent Computation Units: ALU, Multiplier/
Accumulator and Shifter
Single-Cycle Instruction Execution and Multifunction
Instructions
On-Chip Program Memory ROM and Data Memory RAM
Integrated I/O Peripherals: Serial Ports, Timer
FEATURES
25 MIPS, 40 ns Maximum Instruction Rate (5 V)
Separate On-Chip Buses for Program and Data Memory
Program Memory Stores Both Instructions and Data
(Three-Bus Performance)
Dual Data Address Generators with Modulo and
Bit-Reverse Addressing
Efficient Program Sequencing with Zero-Overhead
Looping: Single-Cycle Loop Setup
Double-Buffered Serial Ports with Companding Hardware,
Automatic Data Buffering and Multichannel Operation
Three Edge- or Level-Sensitive Interrupts
Low Power IDLE Instruction
PLCC and MQFP Packages
DSP Microcomputers with ROM
ADSP-216x
FUNCTIONAL BLOCK DIAGRAM
MEMORY
PROGRAM
SEQUENCER
PROGRAM
MEMORY
DATA
MEMORY
DATA ADDRESS
GENERATORS
DAG 1 DAG 2
PROGRAM MEMORY ADDRESS
DATA MEMORY ADDRESS
PROGRAM MEMORY DATA
DATA MEMORY DATA
EXTERNAL
ADDRESS
BUS
EXTERNAL
DATA
BUS
ARITHMETIC UNITS
ALU MAC
SHIFTER
SERIAL PORTS
SPORT 0 SPORT 1
TIMER
ADSP-2100 CORE
Fabricated in a high speed, submicron, double-layer metal
CMOS process, the highest-performance ADSP-216x proces-
sors operate at 25 MHz with a 40 ns instruction cycle time.
Every instruction can execute in a single cycle. Fabrication in
CMOS results in low power dissipation.
The ADSP-2100 Family’s flexible architecture and compre-
hensive instruction set support a high degree of parallelism.
In one cycle the ADSP-216x can perform all of the following
operations:
GENERAL DESCRIPTION
The ADSP-216x Family processors are single-chip micro-
computers optimized for digital signal processing (DSP)
and other high speed numeric processing applications. The
ADSP-216x processors are all built upon a common core with
ADSP-2100. Each processor combines the core DSP architec-
ture—computation units, data address generators and program
sequencer—with features such as on-chip program ROM and
data memory RAM, a programmable timer and two serial ports.
The ADSP-2165/ADSP-2166 also adds program memory and
power-down mode.
This data sheet describes the following ADSP-216x Family
processors:
ADSP-2161/ADSP-2162/
ADSP-2163/ADSP-2164
ADSP-2165/ADSP-2166
Custom ROM-programmed DSPs:
ROM-programmed ADSP-216x
processors with power-down and
larger on-chip memories (12K Pro-
gram Memory ROM, 1K Program
Memory RAM, 4K Data Memory
RAM)
•
Generate the next program address
•
Fetch the next instruction
•
Perform one or two data moves
•
Update one or two data address pointers
•
Perform a computation
•
Receive and transmit data via one or two serial ports
Table I shows the features of each ADSP-216x processor.
The ADSP-216x series are memory-variant versions of the
ADSP-2101 and ADSP-2103 that contain factory-programmed
on-chip ROM program memory. These devices offer different
amounts of on-chip memory for program and data storage.
Table I shows the features available in the ADSP-216x series of
custom ROM-coded processors.
The ADSP-216x products eliminate the need for an external
boot EPROM in your system, and can also eliminate the need
for any external program memory by fitting the entire applica-
tion program in on-chip ROM. These devices thus provide an
excellent option for volume applications where board space and
system cost constraints are of critical concern.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 1999
ADSP-216x
TABLE OF CONTENTS
SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . 1
Development Tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Additional Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
ARCHITECTURE OVERVIEW . . . . . . . . . . . . . . . . . . . . 3
Serial Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
SYSTEM INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Clock Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
PIN FUNCTION DESCRIPTIONS . . . . . . . . . . . . . . . . . . 6
Program Memory Interface . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Program Memory Maps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Data Memory Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Data Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
POWER-DOWN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Power-Down Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Entering Power-Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Exiting Power-Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Low Power IDLE Instruction . . . . . . . . . . . . . . . . . . . . . . . 10
ADSP-216x Prototyping . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Ordering Procedure for ADSP-216x ROM Processors . . . . 10
Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
SPECIFICATIONS–RECOMMENDED OPERATING
CONDITIONS
(ADSP-2161/ADSP-2163/ADSP-2165) . . . . . . . . . . . . . . 13
ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . 13
ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . 13
SPECIFICATIONS–SUPPLY CURRENT AND POWER
(ADSP-2161/ADSP-2163/ADSP-2165) . . . . . . . . . . . . . . 14
POWER DISSIPATION EXAMPLE . . . . . . . . . . . . . . . . . 15
ENVIRONMENTAL CONDITIONS . . . . . . . . . . . . . . . . 15
CAPACITIVE LOADING . . . . . . . . . . . . . . . . . . . . . . . . . 15
SPECIFICATIONS–
(ADSP-2161/ADSP-2163/ADSP-2165) . . . . . . . . . . . . . . 16
TEST CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Output Disable Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Output Enable Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
SPECIFICATIONS–RECOMMENDED OPERATING
CONDITIONS
(ADSP-2162/ADSP-2164/ADSP-2166) . . . . . . . . . . . . . . 17
ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . 17
ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . 17
SPECIFICATIONS–SUPPLY CURRENT AND POWER
(ADSP-2162/ADSP-2164/ADSP-2166) . . . . . . . . . . . . . . 18
POWER DISSIPATION EXAMPLE . . . . . . . . . . . . . . . . . 19
ENVIRONMENTAL CONDITIONS . . . . . . . . . . . . . . . . 19
CAPACITIVE LOADING . . . . . . . . . . . . . . . . . . . . . . . . . 19
TEST CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output Disable Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output Enable Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TIMING PARAMETERS
(ADSP-2161/ADSP-2163/ADSP-2165) . . . . . . . . . . . . . .
GENERAL NOTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TIMING NOTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MEMORY REQUIREMENTS . . . . . . . . . . . . . . . . . . . . . .
CLOCK SIGNALS AND RESET . . . . . . . . . . . . . . . . . . .
INTERRUPTS AND FLAGS . . . . . . . . . . . . . . . . . . . . . .
BUS REQUEST/BUS GRANT . . . . . . . . . . . . . . . . . . . . .
MEMORY READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MEMORY WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SERIAL PORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TIMING PARAMETERS
(ADSP-2162/ADSP-2164/ADSP-2166) . . . . . . . . . . . . . .
GENERAL NOTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TIMING NOTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MEMORY REQUIREMENTS . . . . . . . . . . . . . . . . . . . . . .
CLOCK SIGNALS AND RESET . . . . . . . . . . . . . . . . . . .
INTERRUPTS AND FLAGS . . . . . . . . . . . . . . . . . . . . . . .
BUS REQUEST/BUS GRANT . . . . . . . . . . . . . . . . . . . . .
MEMORY READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MEMORY WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SERIAL PORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PIN CONFIGURATIONS
68-Lead PLCC (ADSP-216x) . . . . . . . . . . . . . . . . . . . . .
80-Lead MQFP (ADSP-216x) . . . . . . . . . . . . . . . . . . . . .
PACKAGE OUTLINE DIMENSIONS
68-Lead PLCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
80-Lead MQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
20
20
20
21
21
21
21
22
23
24
25
26
27
28
28
28
28
29
30
31
32
33
34
35
36
37
38
39
–2–
REV. 0
ADSP-216x
Table I. ADSP-216x ROM-Programmed Processor Features
Feature
Data Memory (RAM)
Program Memory (ROM)
Program Memory (RAM)
Timer
Serial Port 0 (Multichannel)
Serial Port 1
Supply Voltage
Speed Grades
(Instruction Cycle Time)
10.24 MHz
(97.6 ns)
13.00 MHz (76.9
ns)
16.67 MHz
(60 ns)
20.00 MHz (50
ns)
25 MHz
(40 ns)
Packages
68-Lead PLCC
80-Lead MQFP
Temperature Grades
K
Commercial,
0°C to +70°C
B
Industrial,
–40°C to +85°C
Development Tools
2161
1/2K
8K
2162
1/2K
8K
2163
1/2K
4K
2164
1/2K
4K
2165
4K
12K
1K
2166
4K
12K
1K
•
•
•
5V
•
•
•
3.3 V
•
•
•
5V
•
•
•
3.3 V
•
•
•
5V
•
•
•
3.3 V
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
ARCHITECTURE OVERVIEW
The ADSP-216x processors are supported by a complete set of
tools for system development. The ADSP-2100 Family Devel-
opment Software includes C and assembly language tools that
allow programmers to write code for any of the ADSP-216x
processors. The ANSI C compiler generates ADSP-216x assem-
bly source code, while the runtime C library provides ANSI-
standard and custom DSP library routines. The ADSP-216x
assembler produces object code modules that the linker com-
bines into an executable file. The processor simulators provide
an interactive instruction-level simulation with a reconfigurable,
windowed user interface. A PROM splitter utility generates
PROM programmer compatible files.
EZ-ICE
®
in-circuit emulators allow debugging of ADSP-21xx
systems by providing a full range of emulation functions such
as modification of memory and register values and execution
breakpoints. EZ-LAB
®
demonstration boards are complete DSP
systems that execute EPROM-based programs.
The EZ-Kit Lite is a very low-cost evaluation/development
platform that contains both the hardware and software needed
to evaluate the ADSP-21xx architecture.
Additional details and ordering information are available in the
ADSP-2100 Family Software & Hardware Development Tools
data
sheet (ADDS-21xx-TOOLS). This data sheet can be requested
from any Analog Devices sales office or distributor.
Additional Information
Figure 1 shows a block diagram of the ADSP-216x architecture.
The processors contain three independent computational units:
the ALU, the multiplier/accumulator (MAC), and the shifter.
The computational units process 16-bit data directly and have
provisions to support multiprecision computations. The ALU
performs a standard set of arithmetic and logic operations;
division primitives are also supported. The MAC performs
single-cycle multiply, multiply/add, and multiply/subtract opera-
tions. The shifter performs logical and arithmetic shifts, normal-
ization, denormalization, and derive exponent operations. The
shifter can be used to efficiently implement numeric format control
including multiword floating-point representations.
The internal result (R) bus directly connects the computational
units so that the output of any unit may be used as the input of
any unit on the next cycle.
A powerful program sequencer and two dedicated data address
generators ensure efficient use of these computational units.
The sequencer supports conditional jumps, subroutine calls,
and returns in a single cycle. With internal loop counters and
loop stacks, the ADSP-216x executes looped code with zero
overhead—no explicit jump instructions are required to main-
tain the loop.
Two data address generators (DAGs) provide addresses for
simultaneous dual operand fetches (from data memory and
program memory). Each DAG maintains and updates four
address pointers. Whenever the pointer is used to access data
(indirect addressing), it is post-modified by the value of one of
four modify registers. A length value may be associated with
each pointer to implement automatic modulo addressing for
circular buffers. The circular buffering feature is also used by
the serial ports for automatic data transfers to (and from) on-
chip memory.
This data sheet provides a general overview of ADSP-216x
processor functionality. For detailed design information on the
architecture and instruction set, refer to the
ADSP-2100 Family
User’s Manual,
Third Edition, available from Analog Devices.
EZ-ICE and EZ-LAB are registered trademarks of Analog Devices, Inc.
REV. 0
–3–
ADSP-216x
INSTRUCTION
REGISTER
DATA
ADDRESS
GENERATOR
#1
DATA
ADDRESS
GENERATOR
#2
14 PMA BUS
PROGRAM
MEMORY
SRAM
& ROM
DATA
MEMORY
SRAM
BOOT
ADDRESS
GENERATOR
PROGRAM
SEQUENCER
TIMER
24
16
PMA BUS
MUX
14
14 PMA BUS
DMA BUS
EXTERNAL
ADDRESS
BUS
24 PMA BUS
BUS
EXCHANGE
16 PMA BUS
16
PMD BUS
24
MUX
DMD BUS
EXTERNAL
DATA
BUS
INPUT REGS
ALU
OUTPUT REGS
INPUT REGS
MAC
OUTPUT REGS
16
R BUS
INPUT REGS
SHIFTER
OUTPUT REGS
COMPANDING
CIRCUITRY
TRANSMIT REG
RECEIVE REG
SERIAL
PORT 0
5
TRANSMIT REG
RECEIVE REG
SERIAL
PORT 1
5
Figure 1. ADSP-216x Block Diagram
Efficient data transfer is achieved with the use of five internal
buses:
•
•
•
•
•
Program Memory Address (PMA) Bus
Program Memory Data (PMD) Bus
Data Memory Address (DMA) Bus
Data Memory Data (DMD) Bus
Result (R) Bus
external boot memory. Multiple programs can be selected and
loaded from the EPROM with no additional hardware.
The data receive and transmit pins on SPORT1 (Serial Port 1)
can be alternatively configured as a general-purpose input flag
and output flag. You can use these pins for event signalling to
and from an external device.
A programmable interval timer can generate periodic interrupts.
A 16-bit count register (TCOUNT) is decremented every
n
cycles, where
n–1
is a scaling value stored in an 8-bit register
(TSCALE). When the value of the count register reaches zero,
an interrupt is generated and the count register is reloaded from
a 16-bit period register (TPERIOD).
Serial Ports
The two address buses (PMA, DMA) share a single external
address bus, allowing memory to be expanded off-chip, and the
two data buses (PMD, DMD) share a single external data bus.
The
BMS, DMS
and
PMS
signals indicate which memory space
is using the external buses.
Program memory can store both instructions and data, permit-
ting the ADSP-216x to fetch two operands in a single cycle,
one from program memory and one from data memory. The
processor can fetch an operand from on-chip program memory
and the next instruction in the same cycle.
The memory interface supports slow memories and memory-
mapped peripherals with programmable wait state generation.
External devices can gain control of the processor’s buses with
the use of the bus request/grant signals (BR,
BG).
One bus grant execution mode (GO Mode) allows the ADSP-
216x to continue running from internal memory. A second
execution mode requires the processor to halt while buses are
granted.
Each ADSP-216x processor can respond to several different
interrupts. There can be up to three external interrupts,
configured as edge- or level-sensitive. Internal interrupts can be
generated by the timer and serial ports. There is also a master
RESET
signal.
Booting circuitry provides for loading on-chip program memory
automatically from byte-wide external memory. After reset,
three wait states are automatically generated. This allows, for
example, a 60 ns ADSP-2161 to use a 200 ns EPROM as
The ADSP-216x processors include two synchronous serial
ports (SPORTs) for serial communications and multiprocessor
communication. All of the ADSP-216x processors have two
serial ports (SPORT0, SPORT1).
The serial ports provide a complete synchronous serial interface
with optional companding in hardware. A wide variety of
framed or frameless data transmit and receive modes of opera-
tion are available. Each SPORT can generate an internal pro-
grammable serial clock or accept an external serial clock.
Each serial port has a 5-pin interface consisting of the following
signals:
Signal Name
SCLK
RFS
TFS
DR
DT
Function
Serial Clock (I/O)
Receive Frame Synchronization (I/O)
Transmit Frame Synchronization (I/O)
Serial Data Receive
Serial Data Transmit
–4–
REV. 0
ADSP-216x
The ADSP-216x serial ports offer the following capabilities:
Bidirectional—Each
SPORT has a separate, double-buffered
transmit and receive function.
Flexible Clocking—Each
SPORT can use an external serial
clock or generate its own clock internally.
Flexible Framing—The
SPORTs have independent framing
for the transmit and receive functions; each function can run in
a frameless mode or with frame synchronization signals inter-
nally generated or externally generated; frame sync signals may
be active high or inverted, with either of two pulsewidths and
timings.
Different Word Lengths—Each
SPORT supports serial data
word lengths from 3 to 16 bits.
Companding in Hardware—Each
SPORT provides optional
A-law and
µ-law
companding according to CCITT recommen-
dation G.711.
Flexible Interrupt Scheme—Receive
and transmit functions
can generate a unique interrupt upon completion of a data word
transfer.
Autobuffering with Single-Cycle Overhead—Each
SPORT
can automatically receive or transmit the contents of an entire
circular data buffer with only one overhead cycle per data word;
an interrupt is generated after the transfer of the entire buffer is
completed.
Multichannel Capability
(SPORT0
Only)—SPORT0
pro-
vides a multichannel interface to selectively receive or transmit a
24-word or 32-word, time-division multiplexed serial bit stream;
this feature is especially useful for T1 or CEPT interfaces, or as
a network communication scheme for multiple processors.
Alternate Configuration—SPORT1
can be alternatively
configured as two external interrupt inputs (IRQ0,
IRQ1)
and
the Flag In and Flag Out signals (FI, FO).
Interrupts
The ADSP-216x uses a vectored interrupt scheme: when an
interrupt is acknowledged, the processor shifts program control
to the interrupt vector address corresponding to the interrupt
received. Interrupts can be optionally nested so that a higher
priority interrupt can preempt the currently executing interrupt
service routine. Each interrupt vector location is four instruc-
tions in length so that simple service routines can be coded
entirely in this space. Longer service routines require an addi-
tional JUMP or CALL instruction.
Individual interrupt requests are logically ANDed with the bits
in the IMASK register; the highest-priority unmasked interrupt
is then selected.
The interrupt control register,
ICNTL,
allows the external
interrupts to be set as either edge- or level-sensitive. Depending
on Bit 4 in
ICNTL,
interrupt service routines can either be
nested (with higher priority interrupts taking precedence) or be
processed sequentially (with only one interrupt service active at
a time).
The interrupt force and clear register, IFC, is a write-only regis-
ter that contains a force bit and a clear bit for each interrupt.
When responding to an interrupt, the ASTAT, MSTAT and
IMASK status registers are pushed onto the status stack and
the PC counter is loaded with the appropriate vector address.
The status stack is seven levels deep to allow interrupt nesting.
The stack is automatically popped when a return from the inter-
rupt instruction is executed.
Pin Definitions
Pin Function Descriptions show pin definitions for the ADSP-
216x processors. Any inputs not used must be tied to V
DD
.
SYSTEM INTERFACE
Figure 3 shows a typical system for the ADSP-216x with two
serial I/O devices, an optional external program and data
memory. A total of 12K words of data memory and 15K words
of program memory is addressable.
Programmable wait-state generation allows the processors to
easily interface to slow external memories.
The ADSP-216x processors also provide either: one external
interrupt (IRQ2) and two serial ports (SPORT0, SPORT1),
or
three external interrupts (IRQ2,
IRQ1, IRQ0)
and one serial
port (SPORT0).
Clock Signals
The ADSP-216x’s interrupt controller lets the processor re-
spond to interrupts with a minimum of overhead. Up to three
external interrupt input pins,
IRQ0, IRQ1
and
IRQ2,
are pro-
vided.
IRQ2
is always available as a dedicated pin;
IRQ1
and
IRQ0 may be alternately configured as part of Serial Port 1. The
ADSP-216x also supports internal interrupts from the timer and
the serial ports. The interrupts are internally prioritized and
individually maskable (except for
RESET
which is nonmaskable).
The
IRQx
input pins can be programmed for either level- or
edge-sensitivity. The interrupt priorities for each ADSP-216x
processor are shown in Table II.
Table II. Interrupt Vector Addresses and Priority
The ADSP-216x processors’ CLKIN input may be driven by a
crystal or by a TTL-compatible external clock signal. The
CLKIN input may not be halted or changed in frequency during
operation, nor operated below the specified low frequency limit.
If an external clock is used, it should be a TTL-compatible
signal running at the instruction rate. The signal should be
connected to the processor’s CLKIN input; in this case, the
XTAL input must be left unconnected.
Because the ADSP-216x processors include an on-chip oscilla-
tor circuit, an external crystal may also be used. The crystal
should be connected across the CLKIN and XTAL pins, with
two capacitors connected as shown in Figure 2. A parallel-
resonant, fundamental frequency, microprocessor-grade crystal
should be used.
ADSP-216x Interrupt Source
RESET
Startup
IRQ2
or Power-Down
SPORT0 Transmit
SPORT0 Receive
SPORT1 Transmit
or
IRQ1
SPORT1 Receive
or
IRQ0
Timer
Interrupt
Vector Address
0x0000
0x0004
(High Priority)
0x0008
0x000C
0x0010
0x0014
0x0018
(Low Priority)
REV. 0
–5–
