a
FEATURES
Performance
13.3 ns Instruction Cycle Time @ 2.75 V (Internal),
75 MIPS Sustained Performance
Single-Cycle Instruction Execution
Single-Cycle Context Switch
3-Bus Architecture Allows Dual Operand Fetches in
Every Instruction Cycle
Multifunction Instructions
Power-Down Mode Featuring Low CMOS Standby Power
Dissipation with 200 CLKIN Cycle Recovery from
Power-Down Condition
Low Power Dissipation in Idle Mode
DSP
Microcomputer
ADSP-2188M
System Interface
Flexible I/O Structure Allows 2.75 V or 3.3 V Operation;
All Inputs Tolerate up to 3.6 V Regardless of Mode
16-Bit Internal DMA Port for High-Speed Access to
On-Chip Memory (Mode Selectable)
4 MByte Memory Interface for Storage of Data Tables
and Program Overlays (Mode Selectable)
8-Bit DMA to Byte Memory for Transparent Program
and Data Memory Transfers (Mode Selectable)
I/O Memory Interface with 2048 Locations Supports
Parallel Peripherals (Mode Selectable)
Programmable Memory Strobe and Separate I/O
Memory Space Permits “Glueless” System Design
Programmable Wait State Generation
Two Double-Buffered Serial Ports with Companding
Hardware and Automatic Data Buffering
Automatic Booting of On-Chip Program Memory from
Byte-Wide External Memory, e.g., EPROM, or
through Internal DMA Port
Six External Interrupts
13 Programmable Flag Pins Provide Flexible System
Signaling
UART Emulation through Software SPORT Reconfiguration
ICE-Port™ Emulator Interface Supports Debugging in
Final Systems
Integration
ADSP-2100 Family Code Compatible (Easy to Use
Algebraic Syntax), with Instruction Set Extensions
256K Bytes of On-Chip RAM, Configured as
48K Words Program Memory RAM
56K Words Data Memory RAM
Dual-Purpose Program Memory for Both Instruction and
Data Storage
Independent ALU, Multiplier/Accumulator, and Barrel
Shifter Computational Units
Two Independent Data Address Generators
Powerful Program Sequencer Provides Zero Overhead
Looping Conditional Instruction Execution
Programmable 16-Bit Interval Timer with Prescaler
100-Lead LQFP and 144-Ball Mini-BGA
FUNCTIONAL BLOCK DIAGRAM
POWER-DOWN
CONTROL
FULL MEMORY MODE
PROGRAMMABLE
I/O
AND
FLAGS
EXTERNAL
ADDRESS
BUS
EXTERNAL
DATA
BUS
BYTE DMA
CONTROLLER
OR
EXTERNAL
DATA
BUS
TIMER
MEMORY
DATA ADDRESS
GENERATORS
DAG1
DAG2
PROGRAM
SEQUENCER
PROGRAM
MEMORY
48K 24 BIT
DATA
MEMORY
56K 16 BIT
PROGRAM MEMORY ADDRESS
DATA MEMORY ADDRESS
PROGRAM MEMORY DATA
DATA MEMORY DATA
ARITHMETIC UNITS
ALU
MAC
SHIFTER
SERIAL PORTS
SPORT0
SPORT1
INTERNAL
DMA
PORT
HOST MODE
ADSP-2100 BASE
ARCHITECTURE
ICE-Port is a trademark of Analog Devices, Inc.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2000
ADSP-2188M
TABLE OF CONTENTS
FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
FUNCTIONAL BLOCK DIAGRAM . . . . . . . . . . . . . . . . 1
GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . 3
DEVELOPMENT SYSTEM . . . . . . . . . . . . . . . . . . . . . . . 3
Additional Information . . . . . . . . . . . . . . . . . . . . . . . . . . 3
ARCHITECTURE OVERVIEW . . . . . . . . . . . . . . . . . . . . 4
Serial Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
PIN DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Common-Mode Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Memory Interface Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Full Memory Mode Pins (Mode C = 0) . . . . . . . . . . . . . . 7
Host Mode Pins (Mode C = 1) . . . . . . . . . . . . . . . . . . . . 7
Terminating Unused Pins . . . . . . . . . . . . . . . . . . . . . . . . 8
Pin Terminations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
LOW POWER OPERATION . . . . . . . . . . . . . . . . . . . . . . . 9
Power-Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Idle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Slow Idle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
SYSTEM INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Clock Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
RESET
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Power Supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
MODES OF OPERATION . . . . . . . . . . . . . . . . . . . . . . . 11
Setting Memory Mode . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Passive Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Active Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
IACK
Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
MEMORY ARCHITECTURE . . . . . . . . . . . . . . . . . . . . . 12
Program Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Data Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Memory Mapped Registers (New to the
ADSP-2188M) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
I/O Space (Full Memory Mode) . . . . . . . . . . . . . . . . . . . 14
Composite Memory Select (CMS) . . . . . . . . . . . . . . . . . 14
Byte Memory Select (BMS) . . . . . . . . . . . . . . . . . . . . . . 14
Byte Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Byte Memory DMA (BDMA, Full Memory Mode) . . . . 14
Internal Memory DMA Port
(IDMA Port; Host Memory Mode) . . . . . . . . . . . . . . 15
Bootstrap Loading (Booting) . . . . . . . . . . . . . . . . . . . . . 16
IDMA Port Booting . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Bus Request and Bus Grant . . . . . . . . . . . . . . . . . . . . . . 16
Flag I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Instruction Set Description . . . . . . . . . . . . . . . . . . . . . . 17
DESIGNING AN EZ-ICE-COMPATIBLE SYSTEM . . . 17
Target Board Connector for EZ-ICE Probe . . . . . . . . . . 18
Target Memory Interface . . . . . . . . . . . . . . . . . . . . . . . . 18
PM, DM, BM, IOM, AND CM . . . . . . . . . . . . . . . . . . . . 18
Target System Interface Signals . . . . . . . . . . . . . . . . . . . 18
RECOMMENDED OPERATING CONDITIONS . . . . .
ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . .
ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . .
TIMING SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . .
GENERAL NOTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TIMING NOTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MEMORY TIMING SPECIFICATIONS . . . . . . . . . . . .
FREQUENCY DEPENDENCY FOR
TIMING SPECIFICATIONS . . . . . . . . . . . . . . . . . . . .
ENVIRONMENTAL CONDITIONS . . . . . . . . . . . . . . .
POWER DISSIPATION . . . . . . . . . . . . . . . . . . . . . . . . . .
Output Drive Currents . . . . . . . . . . . . . . . . . . . . . . . . . .
Capacitive Loading . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TEST CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output Disable Time . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output Enable Time . . . . . . . . . . . . . . . . . . . . . . . . . . .
Clock Signals and Reset . . . . . . . . . . . . . . . . . . . . . . . . .
Interrupts and Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Bus Request–Bus Grant . . . . . . . . . . . . . . . . . . . . . . . . .
Memory Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Memory Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Serial Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IDMA Address Latch . . . . . . . . . . . . . . . . . . . . . . . . . . .
IDMA Write, Short Write Cycle . . . . . . . . . . . . . . . . . .
IDMA Write, Long Write Cycle . . . . . . . . . . . . . . . . . . .
IDMA Read, Long Read Cycle . . . . . . . . . . . . . . . . . . .
IDMA Read, Short Read Cycle . . . . . . . . . . . . . . . . . . .
IDMA Read, Short Read Cycle in Short Read
Only Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
100-LEAD LQFP PIN CONFIGURATION . . . . . . . . . .
LQFP Package Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . .
144-Ball Mini-BGA Package Pinout . . . . . . . . . . . . . . . . .
Mini-BGA Package Pinout . . . . . . . . . . . . . . . . . . . . . . . .
OUTLINE DIMENSIONS
100-Lead Metric Thin Plastic Quad Flatpack
(LQFP) (ST-100) . . . . . . . . . . . . . . . . . . . . . . . . . . .
OUTLINE DIMENSIONS
144-Ball Mini-BGA (CA-144) . . . . . . . . . . . . . . . . . . . .
ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Tables
19
19
20
20
20
20
20
21
21
21
21
22
23
23
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
40
40
Table I. Interrupt Priority and Interrupt
Vector Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table II. Modes of Operation . . . . . . . . . . . . . . . . . . . . . . 11
Table III. PMOVLAY Bits . . . . . . . . . . . . . . . . . . . . . . . . 12
Table IV. DMOVLAY Bits . . . . . . . . . . . . . . . . . . . . . . . . 13
Table V. Wait States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table VI. Data Formats . . . . . . . . . . . . . . . . . . . . . . . . . . 14
–2–
REV. 0
ADSP-2188M
GENERAL DESCRIPTION
The ADSP-2188M is a single-chip microcomputer optimized
for digital signal processing (DSP) and other high-speed numeric
processing applications.
The ADSP-2188M combines the ADSP-2100 family base archi-
tecture (three computational units, data address generators, and
a program sequencer) with two serial ports, a 16-bit internal DMA
port, a byte DMA port, a programmable timer, Flag I/O, exten-
sive interrupt capabilities, and on-chip program and data memory.
The ADSP-2188M integrates 256K bytes of on-chip memory
configured as 48K words (24-bit) of program RAM, and 56K
words (16-bit) of data RAM. Power-down circuitry is also pro-
vided to meet the low power needs of battery-operated portable
equipment. The ADSP-2188M is available in a 100-lead LQFP
package and 144 Ball Mini-BGA.
In addition, the ADSP-2188M supports new instructions, which
include bit manipulations—bit set, bit clear, bit toggle, bit test—
new ALU constants, new multiplication instruction (× squared),
biased rounding, result-free ALU operations, I/O memory trans-
fers, and global interrupt masking, for increased flexibility.
Fabricated in a high-speed, low-power, CMOS process, the
ADSP-2188M operates with a 13.3 ns instruction cycle time.
Every instruction can execute in a single processor cycle.
The ADSP-2188M’s flexible architecture and comprehensive
instruction set allow the processor to perform multiple opera-
tions in parallel. In one processor cycle, the ADSP-2188M can:
•
•
•
•
•
•
•
•
•
Generate the next program address
Fetch the next instruction
Perform one or two data moves
Update one or two data address pointers
Perform a computational operation
Receive and transmit data through the two serial ports
Receive and/or transmit data through the internal DMA port
Receive and/or transmit data through the byte DMA port
Decrement timer
The EZ-KIT Lite is a hardware/software kit offering a complete
evaluation environment for the ADSP-218x family: an ADSP-
2189M-based evaluation board with PC monitor software plus
assembler, linker, simulator, and PROM splitter software. The
ADSP-2189M EZ-KIT Lite is a low cost, easy to use hardware
platform on which you can quickly get started with your DSP
software design. The EZ-KIT Lite includes the following features:
•
•
•
•
•
•
75 MHz ADSP-2189M
Full 16-Bit Stereo Audio I/O with AD73322 Codec
RS-232 Interface
EZ-ICE Connector for Emulator Control
DSP Demo Programs
Evaluation Suite of VisualDSP
The ADSP-218x EZ-ICE
®
Emulator aids in the hardware
debugging of an ADSP-2188M system. The ADSP-2188M
integrates on-chip emulation support with a 14-pin ICE-Port
interface. This interface provides a simpler target board connec-
tion that requires fewer mechanical clearance considerations
than other ADSP-2100 Family EZ-ICEs. The ADSP-2188M
device need not be removed from the target system when using
the EZ-ICE, nor are any adapters needed. Due to the small
footprint of the EZ-ICE connector, emulation can be supported
in final board designs.
The EZ-ICE performs a full range of functions, including:
•
•
•
•
•
•
•
•
In-target operation
Up to 20 breakpoints
Single-step or full-speed operation
Registers and memory values can be examined and altered
PC upload and download functions
Instruction-level emulation of program booting and execution
Complete assembly and disassembly of instructions
C source-level debugging
This takes place while the processor continues to:
See
Designing An EZ-ICE-Compatible Target System
in the
ADSP-2100 Family EZ-Tools Manual
(ADSP-2181 sections) as
well as the Designing an EZ-ICE-Compatible System section of
this data sheet for the exact specifications of the EZ-ICE target
board connector.
Additional Information
DEVELOPMENT SYSTEM
The ADSP-2100 Family Development Software, a complete set
of tools for software and hardware system development, supports
the ADSP-2188M. The System Builder provides a high-level
method for defining the architecture of systems under develop-
ment. The Assembler has an algebraic syntax that is easy to
program and debug. The Linker combines object files into an
executable file. The Simulator provides an interactive instruction-
level simulation with a reconfigurable user interface to display
different portions of the hardware environment.
This data sheet provides a general overview of ADSP-2188M
functionality. For additional information on the architecture and
instruction set of the processor, refer to the
ADSP-2100 Family
User’s Manual.
For more information about the development
tools, refer to the ADSP-2100 Family Development Tools
data sheet.
EZ-ICE is a registered trademark of Analog Devices, Inc.
REV. 0
–3–
ADSP-2188M
POWER-DOWN
CONTROL
FULL MEMORY MODE
PROGRAMMABLE
I/O
AND
FLAGS
EXTERNAL
ADDRESS
BUS
EXTERNAL
DATA
BUS
BYTE DMA
CONTROLLER
OR
EXTERNAL
DATA
BUS
TIMER
MEMORY
DATA ADDRESS
GENERATORS
DAG1
DAG2
PROGRAM
SEQUENCER
PROGRAM
MEMORY
48K 24 BIT
DATA
MEMORY
56K 16 BIT
PROGRAM MEMORY ADDRESS
DATA MEMORY ADDRESS
PROGRAM MEMORY DATA
DATA MEMORY DATA
ARITHMETIC UNITS
ALU
MAC
SHIFTER
SERIAL PORTS
SPORT0
SPORT1
INTERNAL
DMA
PORT
HOST MODE
ADSP-2100 BASE
ARCHITECTURE
Figure 1. Functional Block Diagram
ARCHITECTURE OVERVIEW
The ADSP-2188M instruction set provides flexible data moves
and multifunction (one or two data moves with a computation)
instructions. Every instruction can be executed in a single
processor cycle. The ADSP-2188M assembly language uses an
algebraic syntax for ease of coding and readability. A compre-
hensive set of development tools supports program development.
Figure 1 is an overall block diagram of the ADSP-2188M. The
processor contains three independent computational units:
the ALU, the multiplier/accumulator (MAC), and the shifter.
The computational units process 16-bit data directly and have
provisions to support multiprecision computations. The ALU
performs a standard set of arithmetic and logic operations;
division primitives are also supported. The MAC performs
single-cycle multiply, multiply/add, and multiply/subtract opera-
tions with 40 bits of accumulation. The shifter performs logical
and arithmetic shifts, normalization, denormalization, and
derive exponent operations.
The shifter can be used to efficiently implement numeric
format control, including multiword and block floating-point
representations.
The internal result (R) bus connects the computational units so
that the output of any unit may be the input of any unit on the
next cycle.
A powerful program sequencer and two dedicated data address
generators ensure efficient delivery of operands to these computa-
tional units. The sequencer supports conditional jumps, subroutine
calls, and returns in a single cycle. With internal loop counters
and loop stacks, the ADSP-2188M executes looped code with
zero overhead; no explicit jump instructions are required to
maintain loops.
Two data address generators (DAGs) provide addresses for
simultaneous dual operand fetches (from data memory and
program memory). Each DAG maintains and updates four
address pointers. Whenever the pointer is used to access data
(indirect addressing), it is post-modified by the value of one of
four possible modify registers. A length value may be associated
with each pointer to implement automatic modulo addressing
for circular buffers.
Efficient data transfer is achieved with the use of five
internal buses:
•
•
•
•
•
Program Memory Address (PMA) Bus
Program Memory Data (PMD) Bus
Data Memory Address (DMA) Bus
Data Memory Data (DMD) Bus
Result (R) Bus
The two address buses (PMA and DMA) share a single external
address bus, allowing memory to be expanded off-chip, and the
two data buses (PMD and DMD) share a single external data
bus. Byte memory space and I/O memory space also share the
external buses.
Program memory can store both instructions and data, permit-
ting the ADSP-2188M to fetch two operands in a single cycle,
one from program memory and one from data memory. The
ADSP-2188M can fetch an operand from program memory and
the next instruction in the same cycle.
In lieu of the address and data bus for external memory connec-
tion, the ADSP-2188M may be configured for 16-bit Internal
DMA port (IDMA port) connection to external systems. The
IDMA port is made up of 16 data/address pins and five control
pins. The IDMA port provides transparent, direct access to the
DSPs on-chip program and data RAM.
An interface to low-cost byte-wide memory is provided by the
Byte DMA port (BDMA port). The BDMA port is bidirectional
and can directly address up to four megabytes of external RAM
or ROM for off-chip storage of program overlays or data tables.
The byte memory and I/O memory space interface supports slow
memories and I/O memory-mapped peripherals with program-
mable wait state generation. External devices can gain control of
–4–
REV. 0
ADSP-2188M
external buses with bus request/grant signals (BR,
BGH,
and
BG).
One execution mode (Go Mode) allows the ADSP-2188M to
continue running from on-chip memory. Normal execution
mode requires the processor to halt while buses are granted.
The ADSP-2188M can respond to eleven interrupts. There can
be up to six external interrupts (one edge-sensitive, two level-
sensitive, and three configurable) and seven internal interrupts
generated by the timer, the serial ports (SPORTs), the Byte DMA
port, and the power-down circuitry. There is also a master
RESET
signal. The two serial ports provide a complete synchro-
nous serial interface with optional companding in hardware and
a wide variety of framed or frameless data transmit and receive
modes of operation.
Each port can generate an internal programmable serial clock or
accept an external serial clock.
The ADSP-2188M provides up to 13 general-purpose flag pins.
The data input and output pins on SPORT1 can be alternatively
configured as an input flag and an output flag. In addition, eight
flags are programmable as inputs or outputs, and three flags are
always outputs.
A programmable interval timer generates periodic interrupts.
A 16-bit count register (TCOUNT) decrements every n pro-
cessor cycle, where n is a scaling value stored in an 8-bit register
(TSCALE). When the value of the count register reaches zero,
an interrupt is generated and the count register is reloaded from
a 16-bit period register (TPERIOD).
Serial Ports
• SPORTs can use an external serial clock or generate their
own serial clock internally.
• SPORTs have independent framing for the receive and trans-
mit sections. Sections run in a frameless mode or with frame
synchronization signals internally or externally generated.
Frame sync signals are active high or inverted, with either of
two pulsewidths and timings.
• SPORTs support serial data word lengths from 3 to 16 bits
and provide optional A-law and
µ-law
companding according
to CCITT recommendation G.711.
• SPORT receive and transmit sections can generate unique
interrupts on completing a data word transfer.
• SPORTs can receive and transmit an entire circular buffer of
data with only one overhead cycle per data word. An interrupt
is generated after a data buffer transfer.
• SPORT0 has a multichannel interface to selectively receive
and transmit a 24 or 32 word, time- division multiplexed,
serial bitstream.
• SPORT1 can be configured to have two external interrupts
(IRQ0 and
IRQ1)
and the FI and FO signals. The internally
generated serial clock may still be used in this configuration.
PIN DESCRIPTIONS
The ADSP-2188M incorporates two complete synchronous
serial ports (SPORT0 and SPORT1) for serial communications
and multiprocessor communication.
Here is a brief list of the capabilities of the ADSP-2188M
SPORTs. For additional information on Serial Ports, refer to
the
ADSP-2100 Family User’s Manual.
• SPORTs are bidirectional and have a separate, double-
buffered transmit and receive section.
The ADSP-2188M is available in a 100-lead LQFP package
and a 144-Ball Mini-BGA package. In order to maintain maxi-
mum functionality and reduce package size and pin count, some
serial port, programmable flag, interrupt and external bus pins
have dual, multiplexed functionality. The external bus pins are
configured during
RESET
only, while serial port pins are soft-
ware configurable during program execution. Flag and interrupt
functionality is retained concurrently on multiplexed pins. In
cases where pin functionality is reconfigurable, the default state is
shown in plain text; alternate functionality is shown in italics.
REV. 0
–5–
