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PERFORMANCE FEATURES
6.25 ns Instruction Cycle Time, for up to 160 MIPS
Sustained Performance
ADSP-218x Family Code Compatible with the Same
Easy to Use Algebraic Syntax
Single-Cycle Instruction Execution
Single-Cycle Context Switch between Two Sets of Com-
putation and Memory Instructions
Instruction Cache Allows Dual Operand Fetches in Every
Instruction Cycle
DSP Microcomputer
ADSP-2191M
Multifunction Instructions
Pipelined Architecture Supports Efficient Code
Execution
Architectural Enhancements for Compiled C and C++
Code Efficiency
Architectural Enhancements beyond ADSP-218x Family
are Supported with Instruction Set Extensions for
Added Registers, and Peripherals
Flexible Power Management with User-Selectable
Power-Down and Idle Modes
FUNCTIONAL BLOCK DIAGRAM
INTERNAL MEMORY
FOUR INDEPENDENT BLOCKS
ADSP-219x
DSP CORE
CACHE
64 24-BIT
BLOCK0
BLOCK1
BLOCK2
BLOCK3
24 BIT
ADDRESS
DATA
24 BIT
ADDRESS
DATA
16 BIT
DATA
ADDRESS
16 BIT
DATA
ADDRESS
JTAG
TEST &
EMULATION
6
4
DAG1
4 16
4
DAG2
4 16
PROGRAM
SEQUENCER
EXTERNAL PORT
PM ADDRESS BUS
24
I/O ADDRESS
18
ADDR BUS
MUX
24
DMA
CONNECT
PM DATA BUS
24
16
16
I/O DATA
I/O PROCESSOR
DATA BUS
MUX
16
DMA ADDRESS
24
DMA DATA
22
DM ADDRESS BUS
24
PX
DM DATA BUS
DATA
REGISTER
FILE
INPUT
REGISTERS
RESULT
REGISTERS
MULT
16
16-BIT
BARREL
SHIFTER
ALU
I/O REGISTERS
(MEMORY-MAPPED)
CONTROL
STATUS
BUFFERS
DMA
CONTROLLER
24
HOST PORT
18
SERIAL PORTS
(3)
6
SPI PORTS
(2)
2
UART PORT
(1)
3
SYSTEM INTERRUPT CONTROLLER
PROGRAMMABLE
FLAGS (16)
TIMERS (3)
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
One Technology Way, P.O.Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel:781/329-4700
www.analog.com
Fax:781/326-8703
©
Analog Devices, Inc., 2002
ADSP-2191M
INTEGRATION FEATURES
160K Bytes On-Chip RAM Configured as 32K Words 24-Bit
Memory RAM and 32K Words 16-Bit Memory RAM
Dual-Purpose 24-Bit Memory for Both Instruction and
Data Storage
Independent ALU, Multiplier/Accumulator, and Barrel
Shifter Computational Units with Dual 40-Bit
Accumulators
Unified Memory Space Allows Flexible Address Genera-
tion, Using Two Independent DAG Units
Powerful Program Sequencer Provides Zero-Overhead
Looping and Conditional Instruction Execution
Enhanced Interrupt Controller Enables Programming of
Interrupt Priorities and Nesting Modes
SYSTEM INTERFACE FEATURES
Host Port with DMA Capability for Glueless 8- or 16-Bit
Host Interface
16-Bit External Memory Interface for up to 16M Words of
Addressable Memory Space
Three Full-Duplex Multichannel Serial Ports, with
Support for H.100 and up to 128 TDM Channels with
A-Law and -Law Companding Optimized for Telecom-
munications Systems
Two SPI-Compatible Ports with DMA Support
UART Port with DMA Support
16 General-Purpose I/O Pins with Integrated Interrupt
Support
Three Programmable Interval Timers with PWM
Generation, PWM Capture/Pulsewidth Measurement,
and External Event Counter Capabilities
Up to 11 DMA Channels Can Be Active at Any Given Time
for High I/O Throughput
On-Chip Boot ROM for Automatic Booting from External
8- or 16-Bit Host Device, SPI ROM, or UART with
Autobaud Detection
Programmable PLL Supports 1 to 32 Input Frequency
Multiplication and Can Be Altered during Runtime
IEEE JTAG Standard 1149.1 Test Access Port Supports
On-Chip Emulation and System Debugging
2.5 V Internal Operation and 3.3 V I/O
144-Lead LQFP and 144-Ball Mini-BGA Packages
TABLE OF CONTENTS
GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . .3
DSP Core Architecture . . . . . . . . . . . . . . . . . . . . . . . .3
DSP Peripherals Architecture . . . . . . . . . . . . . . . . . . .4
Memory Architecture . . . . . . . . . . . . . . . . . . . . . . . . .5
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
DMA Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Host Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
DSP Serial Ports (SPORTs) . . . . . . . . . . . . . . . . . . . .8
Serial Peripheral Interface (SPI) Ports . . . . . . . . . . . . .9
UART Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Programmable Flag (PFx) Pins . . . . . . . . . . . . . . . . . .9
Low Power Operation . . . . . . . . . . . . . . . . . . . . . . . .10
Clock Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Power Supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Booting Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Bus Request and Bus Grant . . . . . . . . . . . . . . . . . . .12
Instruction Set Description . . . . . . . . . . . . . . . . . . . .13
Development Tools . . . . . . . . . . . . . . . . . . . . . . . . . .13
Additional Information . . . . . . . . . . . . . . . . . . . . . . .15
PIN FUNCTION DESCRIPTIONS . . . . . . . . . . . . . .15
SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . .18
ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . .19
ESD SENSITIVITY . . . . . . . . . . . . . . . . . . . . . . . . .19
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . .19
TIMING SPECIFICATIONS . . . . . . . . . . . . . . . . .20
Output Drive Currents . . . . . . . . . . . . . . . . . . . . . . .40
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . .40
Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
Environmental Conditions . . . . . . . . . . . . . . . . . . . .41
144-Lead LQFP Pinout . . . . . . . . . . . . . . . . . . . . . .43
144-Lead Mini-BGA Pinout . . . . . . . . . . . . . . . . . . .45
OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . .47
ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . .48
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
–2–
REV. A
ADSP-2191M
GENERAL DESCRIPTION
The ADSP-2191M DSP is a single-chip microcomputer
optimized for digital signal processing (DSP) and other high
speed numeric processing applications.
The ADSP-2191M combines the ADSP-219x family base
architecture (three computational units, two data address gener-
ators, and a program sequencer) with three serial ports, two
SPI-compatible ports, one UART port, a DMA controller, three
programmable timers, general-purpose Programmable Flag
pins, extensive interrupt capabilities, and on-chip program and
data memory spaces.
The ADSP-2191M architecture is code-compatible with DSPs
of the ADSP-218x family. Although the architectures are
compatible, the ADSP-2191M architecture has a number of
enhancements over the ADSP-218x architecture. The enhance-
ments to computational units, data address generators, and
program sequencer make the ADSP-2191M more flexible and
even easier to program.
Indirect addressing options provide addressing flexibility—
premodify with no update, pre- and post-modify by an immediate
8-bit, two’s-complement value and base address registers for
easier implementation of circular buffering.
The ADSP-2191M integrates 64K words of on-chip memory
configured as 32K words (24-bit) of program RAM, and
32K words (16-bit) of data RAM. Power-down circuitry is also
provided to reduce power consumption. The ADSP-2191M is
available in 144-lead LQFP and 144-ball mini-BGA packages.
Fabricated in a high speed, low power, CMOS process, the
ADSP-2191M operates with a 6.25 ns instruction cycle time
(160 MIPS). All instructions, except single-word instructions,
execute in one processor.
The ADSP-2191M’s flexible architecture and comprehensive
instruction set support multiple operations in parallel. For
example, in one processor cycle, the ADSP-2191M can:
•
Generate an address for the next instruction fetch
•
Fetch the next instruction
•
Perform one or two data moves
•
Update one or two data address pointers
•
Perform a computational operation
These operations take place while the processor continues to:
•
Receive and transmit data through two serial ports
•
Receive and/or transmit data from a Host
•
Receive or transmit data through the UART
•
Receive or transmit data over two SPI ports
•
Access external memory through the external memory
interface
•
Decrement the timers
DSP Core Architecture
uses an algebraic syntax for ease of coding and readability. A
comprehensive set of development tools supports program
development.
The functional block diagram
on Page 1
shows the architecture
of the ADSP-219x core. It contains three independent compu-
tational units: the ALU, the multiplier/accumulator (MAC), and
the shifter. The computational units process 16-bit data from the
register file and have provisions to support multiprecision com-
putations. The ALU performs a standard set of arithmetic and
logic operations; division primitives are also supported. The
MAC performs single-cycle multiply, multiply/add, and multi-
ply/subtract operations. The MAC has two 40-bit accumulators,
which help with overflow. The shifter performs logical and arith-
metic shifts, normalization, denormalization, and derive
exponent operations. The shifter can be used to efficiently
implement numeric format control, including multiword and
block floating-point representations.
Register-usage rules influence placement of input and results
within the computational units. For most operations, the com-
putational units’ data registers act as a data register file,
permitting any input or result register to provide input to any unit
for a computation. For feedback operations, the computational
units let the output (result) of any unit be input to any unit on
the next cycle. For conditional or multifunction instructions,
there are restrictions on which data registers may provide inputs
or receive results from each computational unit. For more infor-
mation, see the
ADSP-219x DSP Instruction Set Reference.
A powerful program sequencer controls the flow of instruction
execution. The sequencer supports conditional jumps, subrou-
tine calls, and low interrupt overhead. With internal loop
counters and loop stacks, the ADSP-2191M executes looped
code with zero overhead; no explicit jump instructions are
required to maintain loops.
Two data address generators (DAGs) provide addresses for
simultaneous dual operand fetches (from data memory and
program memory). Each DAG maintains and updates four
16-bit address pointers. Whenever the pointer is used to access
data (indirect addressing), it is pre- or post-modified by the value
of one of four possible modify registers. A length value and base
address may be associated with each pointer to implement
automatic modulo addressing for circular buffers. Page registers
in the DAGs allow circular addressing within 64K-word bound-
aries of each of the 256 memory pages, but these buffers may not
cross page boundaries. Secondary registers duplicate all the
primary registers in the DAGs; switching between primary and
secondary registers provides a fast context switch.
Efficient data transfer in the core is achieved with the use of
internal buses:
•
Program Memory Address (PMA) Bus
•
Program Memory Data (PMD) Bus
•
Data Memory Address (DMA) Bus
•
Data Memory Data (DMD) Bus
•
DMA Address Bus
•
DMA Data Bus
The ADSP-2191M instruction set provides flexible data moves
and multifunction (one or two data moves with a computation)
instructions. Every single-word instruction can be executed in a
single processor cycle. The ADSP-2191M assembly language
REV. A
–3–
ADSP-2191M
The two address buses (PMA and DMA) share a single external
address bus, allowing memory to be expanded off-chip, and the
two data buses (PMD and DMD) share a single external data
bus. Boot memory space and I/O memory space also share the
external buses.
Program memory can store both instructions and data, permit-
ting the ADSP-2191M to fetch two operands in a single cycle,
one from program memory and one from data memory. The
DSP’s dual memory buses also let the ADSP-219x core fetch an
operand from data memory and the next instruction from
program memory in a single cycle.
DSP Peripherals Architecture
ADSP-2191M
CLOCK
OR
CRYSTAL
TIMER
OUT OR
CAPTURE
CLOCK
MULTIPLY
AND
RANGE
BOOT
AND OP
MODE
CLKIN
XTAL
CLKOUT
ADDR21–0
DATA15–8
TMR2–0
DATA7–0
MS3–0
MSEL6–0/PF6–0
DF/PF7
BYPASS
BMODE1–0
OPMODE
RD
WR
ACK
CONTROL
ADDRESS
DATA
EXTERNAL
MEMORY
(OPTIONAL)
ADDR21–0
DATA15–8
DATA7–0
CS
OE
WE
ACK
BOOT
MEMORY
(OPTIONAL)
The functional block diagram
on Page 1
shows the DSP’s
on-chip peripherals, which include the external memory inter-
face, Host port, serial ports, SPI-compatible ports, UART port,
JTAG test and emulation port, timers, flags, and interrupt con-
troller. These on-chip peripherals can connect to off-chip devices
as shown in
Figure 1.
The ADSP-2191M has a 16-bit Host port with DMA capability
that lets external Hosts access on-chip memory. This 24-pin
parallel port consists of a 16-pin multiplexed data/address bus
and provides a lowservice overhead data move capability. Con-
figurable for 8 or 16 bits, this port provides a glueless interface
to a wide variety of 8- and 16-bit microcontrollers. Two
chip-selects provide Hosts access to the DSP’s entire memory
map. The DSP is bootable through this port.
The ADSP-2191M also has an external memory interface that is
shared by the DSP’s core, the DMA controller, and DMA
capable peripherals, which include the UART, SPORT0,
SPORT1, SPORT2, SPI0, SPI1, and the Host port. The external
port consists of a 16-bit data bus, a 22-bit address bus, and
control signals. The data bus is configurable to provide an 8- or
16-bit interface to external memory. Support for word packing
lets the DSP access 16- or 24-bit words from external memory
regardless of the external data bus width. When configured for
an 8-bit interface, the unused eight lines provide eight program-
mable, bidirectional general-purpose Programmable Flag lines,
six of which can be mapped to software condition signals.
The memory DMA controller lets the ADSP-2191M move data
and instructions from between memory spaces: internal-to-exter-
nal, internal-to-internal, and external-to-external. On-chip
peripherals can also use this controller for DMA transfers.
The ADSP-2191M can respond to up to seventeen interrupts at
any given time: three internal (stack, emulator kernel, and
power-down), two external (emulator and reset), and twelve user-
defined (peripherals) interrupts. The programmer assigns a
peripheral to one of the 12 user-defined interrupts. The priority
of each peripheral for interrupt service is determined by these
assignments.
There are three serial ports on the ADSP-2191M that provide a
complete synchronous, full-duplex serial interface. This interface
includes optional companding in hardware as well as a wide
variety of framed or frameless data transmit and receive modes
SPORT0
TCLK0
TFS0
SERIAL
DEVICE
(OPTIONAL)
ADDR21–0
DATA15–8
DATA7–0
BMS
CS
OE
WE
ACK
BR
BG
BGH
EXTERNAL
I/O MEMORY
(OPTIONAL)
DT0
RCLK0
RFS0
DR0
SPORT1
TCLK1
TFS1
SERIAL
DEVICE
(OPTIONAL)
DT1
RCLK1
RFS1
DR1
SPORT2
TCLK2/SCK0
TFS2/MOSI0
SPI0
IOMS
ADDR17–0
DATA15–8
DATA7–0
CS
OE
WE
ACK
HOST
PROCESSOR
SPI1
HAD15–0
HA16
UART
HCMS
HCIOMS
HRD
HWR
(OPTIONAL)
SERIAL
DEVICE
(OPTIONAL)
DT2/MISO0
RCLK2/SCK1
RFS2/MOSI1
DR2/MISO1
ADDR15–0/
DATA15–0
ADDR16
CS0
CS1
RD
WR
ACK
ALE
UART
DEVICE
(OPTIONAL)
RXD
TXD
RESET
6
JTAG
HACK
HALE
HACK_P
Figure 1. System Diagram
of operation. Each serial port can transmit or receive an internal
or external, programmable serial clock and frame syncs. Each
serial port supports 128-channel Time Division Multiplexing.
The ADSP-2191M provides up to sixteen general-purpose I/O
pins, which are programmable as either inputs or outputs. Eight
of these pins are dedicated-general purpose Programmable Flag
pins. The other eight of them are multifunctional pins, acting as
general-purpose I/O pins when the DSP connects to an 8-bit
external data bus and acting as the upper eight data pins when
the DSP connects to a 16-bit external data bus. These Program-
mable Flag pins can implement edge- or level-sensitive
interrupts, some of which can be used to base the execution of
conditional instructions.
–4–
REV. A
单片机
