Precision Analog Microcontroller
ARM7TDMI MCU with 12-Bit ADC and DDS DAC
ADuC7128/ADuC7129
FEATURES
Analog I/O
Multichannel, 12-bit, 1 MSPS ADC
Up to 14 analog-to-digital converter (ADC) channels
Fully differential and single-ended modes
0 to V
REF
analog input range
10-bit digital-to-analog converter (DAC)
32-bit 21 MHz direct digital synthesis (DDS)
Current-to-voltage (I/V) conversion
Integrated second-order low-pass filter (LPF)
DDS input to DAC
100 Ω line driver
On-chip voltage reference
On-chip temperature sensor (±3°C)
Voltage comparator
Microcontroller
ARM7TDMI core, 16-/32-bit RISC architecture
JTAG port supports code download and debug
External watch crystal/clock source
41.78 MHz PLL with 8-way programmable divider
Optional trimmed on-chip oscillator
Memory
126 kB Flash/EE memory, 8 kB SRAM
In-circuit download, JTAG-based debug
Software triggered in-circuit reprogrammability
On-chip peripherals
2× UART, 2× I
2
C and SPI serial I/O
Up to 40-pin GPIO port
5× general-purpose timers
Wake-up and watchdog timers (WDT)
Power supply monitor
16-bit PWM generator
Quadrature encoder
Programmable logic array (PLA)
Power
Specified for 3 V operation
Active mode
11 mA (@ 5.22 MHz)
45 mA (@ 41.78 MHz)
Packages and temperature range
64-lead 9 mm × 9 mm LFCSP package, −40°C to 125°C
64-lead LQFP, −40°C to +125°C
80-lead LQFP, −40°C to +125°C
Tools
Low cost QuickStart development system
Full third-party support
FUNCTIONAL BLOCK DIAGRAM
DACGND
DACV
DD
GND
REF
IOGND
IOGND
AGND
DGND
IOV
DD
IOV
DD
AV
DD
LV
DD
ADC0
MUX
T/H
TEMP
SENSOR
12-BIT SAR
ADC 1MSPS
DDS
10-BIT
IOUT DAC
I/V
I/V
LPF
VDAC
OUT
LD1TX
LD2TX
CMP0
CMP1
CMP
OUT
V
REF
+
–
BAND GAP
REFERENCE
ADuC7129
ARM7TDMI-BASED MCU
WITH ADDITIONAL PERIPHERALS
5 GEN PURPOSE
2 kBYTES
TIMERS
62 kBYTES 64 kBYTES 8192 BYTES
WAKE-UP/
FLASH/EE FLASH/EE
SRAM
RTC TIMER
(32k ×
(31k ×
(2k ×
16 BITS)
16 BITS)
32 BITS)
INTERRUPT
CONTROLLER
GPIO
JTAG PLA SPI I
2
C UART0 UART1 CONTROL
JTAG
P0.0 P0.7
P1.0 P1.7
P2.0 P2.7
P3.0 P3.3
PWM1
PWM2
PWM3
PWM4
PWM5
PWM6
S1
S2
06020-001
PWM
RST
XCLKI
XCLKO
XCLK
POR
OSC/PLL
PSM
QUAD
ENCODER
Figure 1.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2007 Analog Devices, Inc. All rights reserved.
ADuC7128/ADuC7129
TABLE OF CONTENTS
Features .............................................................................................. 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
General Description ......................................................................... 3
Specifications..................................................................................... 4
Timing Specifications .................................................................. 8
Absolute Maximum Ratings.......................................................... 15
ESD Caution................................................................................ 15
Pin Configuration and Function Descriptions........................... 16
Typical Performance Characteristics ........................................... 21
Terminology .................................................................................... 24
ADC Specifications .................................................................... 24
DAC Specifications..................................................................... 24
Overview of the ARM7TDMI Core............................................. 25
Thumb Mode (T)........................................................................ 25
Long Multiply (M)...................................................................... 25
EmbeddedICE (I) ....................................................................... 25
Exceptions ................................................................................... 25
ARM Registers ............................................................................ 25
Interrupt Latency........................................................................ 26
Memory Organization ................................................................... 27
Flash/EE Memory....................................................................... 27
SRAM ........................................................................................... 27
Memory Mapped Registers ....................................................... 27
Complete MMR Listing............................................................. 28
ADC Circuit Overview .................................................................. 32
ADC Transfer Function............................................................. 32
Typical Operation....................................................................... 33
Converter Operation.................................................................. 36
Driving the Analog Inputs ........................................................ 37
Temperature Sensor ................................................................... 37
Band Gap Reference................................................................... 38
Nonvolatile Flash/EE Memory ..................................................... 39
Flash/EE Memory Overview..................................................... 39
Flash/EE Memory....................................................................... 39
Flash/EE Memory Security ....................................................... 40
Flash/EE Control Interface........................................................ 40
Execution Time from SRAM and FLASH/EE........................ 43
Reset and Remap ........................................................................ 44
Other Analog Peripherals.............................................................. 45
DAC.............................................................................................. 45
DDS .............................................................................................. 46
Power Supply Monitor ............................................................... 47
Comparator ................................................................................. 47
Oscillator and PLL—Power Control........................................ 49
Digital Peripherals.......................................................................... 51
PWM General Overview........................................................... 51
PWM Convert Start Control .................................................... 52
General-Purpose I/O ................................................................. 55
Serial Port Mux........................................................................... 57
UART Serial Interface................................................................ 57
Serial Peripheral Interface......................................................... 63
I
2
C-Compatible Interfaces......................................................... 65
I
2
C Registers ................................................................................ 65
Programmable Logic Array (PLA)........................................... 69
Processor Reference Peripherals................................................... 72
Interrupt System ......................................................................... 72
Timers .......................................................................................... 73
Timer0—Lifetime Timer........................................................... 73
Timer1—General-Purpose Timer ........................................... 75
Timer2—Wake-Up Timer......................................................... 77
Timer3—Watchdog Timer........................................................ 79
Timer4—General-Purpose Timer ........................................... 81
External Memory Interfacing ................................................... 83
Timing Diagrams ....................................................................... 84
Hardware Design Considerations ................................................ 87
Power Supplies ............................................................................ 87
Grounding and Board Layout Recommendations................. 87
Clock Oscillator.......................................................................... 88
Power-On Reset Operation....................................................... 89
Development Tools......................................................................... 90
In-Circuit Serial Downloader................................................... 90
Outline Dimensions ....................................................................... 91
Ordering Guide .......................................................................... 92
REVISION HISTORY
4/07—Revision 0: Initial Version
Rev. 0 | Page 2 of 92
ADuC7128/ADuC7129
GENERAL DESCRIPTION
The ADuC7128/ADuC7129 are fully integrated, 1 MSPS, 12-bit
data acquisition systems incorporating a high performance, multi-
channel analog-to-digital converter (ADC), DDS with line
driver, 16-/32-bit MCU, and Flash/EE memory on a single chip.
The ADC consists of up to 14 single-ended inputs. The ADC
can operate in single-ended or differential input modes. The
ADC input voltage is 0 to V
REF
. Low drift band gap reference,
temperature sensor, and voltage comparator complete the ADC
peripheral set.
The ADuC7128/ADuC7129 integrate a differential line driver
output. This line driver transmits a sine wave whose values are
calculated by an on-chip DDS or a voltage output determined
by the DACDAT MMR.
The devices operate from an on-chip oscillator and PLL, generating
an internal high frequency clock of 41.78 MHz. This clock is
routed through a programmable clock divider from which the
MCU core clock operating frequency is generated.
The microcontroller core is an ARM7TDMI®, 16-/32-bit
reduced instruction set computer (RISC), offering up to
41 MIPS peak performance. There are 126 kB of nonvolatile
Flash/EE provided on-chip, as well as 8 kB of SRAM. The
ARM7TDMI core views all memory and registers as a single
linear array.
On-chip factory firmware supports in-circuit serial download
via the UART serial interface port, and nonintrusive emulation
is also supported via the JTAG interface. These features are
incorporated into a low cost QuickStart™ development system
supporting this MicroConverter® family.
The parts operate from 3.0 V to 3.6 V and are specified over an
industrial temperature range of −40°C to +125°C. When operating
at 41.78 MHz, the power dissipation is 135 mW. The line driver
output, if enabled, consumes an additional 30 mW.
Rev. 0 | Page 3 of 92
ADuC7128/ADuC7129
SPECIFICATIONS
AV
DD
= IOV
DD
= 3.0 V to 3.6 V, V
REF
= 2.5 V internal reference, f
CORE
= 41.78 MHz. All specifications T
A
= T
MAX
to T
MIN
, unless
otherwise noted.
Table 1.
Parameter
ADC CHANNEL SPECIFICATIONS
ADC Power-Up Time
DC Accuracy
1, 2
Resolution
Integral Nonlinearity
3
Min
Typ
5
12
±0.7
±0.7
±2.0
±0.5
±0.6
1
±2.0
±1.5
+1/−0.9
Max
Unit
μs
Bits
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
F
IN
= 10 kHz sine wave, f
SAMPLE
= 1 MSPS
69
−78
−75
−80
−60
dB
dB
dB
dB
dB
Test Conditions/Comments
Eight acquisition clocks and fADC/2
Differential Nonlinearity
3
DC Code Distribution
ENDPOINT ERRORS
4
Offset Error
Offset Error Match
Gain Error
Gain Error Match
DYNAMIC PERFORMANCE
Signal-to-Noise Ratio (SNR)
Total Harmonic Distortion (THD)
Peak Harmonic or Spurious Noise
Channel-to-Channel Crosstalk
Crosstalk Between Channel 12 and
Channel 13
ANALOG INPUT
Input Voltage Ranges
Differential Mode
5
Single-Ended Mode
Leakage Current
Input Capacitance
ON-CHIP VOLTAGE REFERENCE
Output Voltage
Accuracy
Reference Drop When DAC Enabled
Reference Temperature Coefficient
Power Supply Rejection Ratio
Output Impedance
Internal V
REF
Power-On Time
EXTERNAL REFERENCE INPUT
6
Input Voltage Range
Input Impedance
DAC CHANNEL SPECIFICATIONS
VDAC Output
Voltage Swing
2.5 V internal reference 85°C to 125°C only
2.5 V internal reference −40°C to +85°C
1.0 V external reference
2.5 V internal reference
1.0 V external reference
ADC input is a dc voltage
±5
±1
±5
±1
±1
20
2.5
V
CM
± V
REF
/2
0 to V
REF
±15
±3
V
V
μA
μA
pF
V
mV
mV
ppm/°C
dB
Ω
ms
V
kΩ
85°C to 125°C only
−40°C to +85°C
During ADC acquisition
0.47 μF from V
REF
to AGND
Measured at T
A
= 25°C
Reference drop when DAC enabled
±2.5
9
±40
80
40
1
0.625
38
AV
DD
(0.33 × V
REF
±
0.2 × V
REF
) ×
1.33
7
1
10
Rev. 0 | Page 4 of 92
R
L
= 5 kΩ, C
L
= 100 pF
V
REF
is the internal 2.5 V reference
I/V Output Resistance
Low-Pass Filter 3 dB Point
Resolution
Ω
MHz
Bits
V mode selected
2-pole at 1.5 MHz and 2 MHz
ADuC7128/ADuC7129
Parameter
Relative Accuracy
Differential Nonlinearity, +VE
Differential Nonlinearity, −VE
Offset Error
Gain Error
Voltage Output Settling Time
to 0.1%
Line Driver Output
Min
Typ
±2
0.35
−0.15
Max
Unit
LSB
LSB
LSB
mV
mV
μs
Test Conditions/Comments
−190
+150
5
Total Harmonic Distortion
Output Voltage Swing
COMMON MODE
AC Mode
−52
±1.768
1.65
dB
V rms
V
As measured into a range of specified loads
(see Figure 2) at LD1TX and LD2TX, unless
otherwise noted
PLM operating at 691.2 kHz
DC Mode
1.5
V
DIFFERENTIAL INPUT IMPEDANCE
Leakage Current LD1TX, LD2TX
Short-Circuit Current
Line Driver Tx Power-Up Time
COMPARATOR
Input Offset Voltage
Input Bias Current
Input Voltage Range
Input Capacitance
Hysteresis
3, 5
Response Time
TEMPERATURE SENSOR
Voltage Output at 25°C
Voltage Temperature Coefficient
Accuracy
POWER SUPPLY MONITOR (PSM)
IOV
DD
Trip Point Selection
Power Supply Trip Point Accuracy
GLITCH IMMUNITY ON RST PIN
3
WATCHDOG TIMER (WDT)
Timeout Period
FLASH/EE MEMORY
Endurance
Data Retention
DIGITAL INPUTS
Logic 1 Input Current (Leakage
Current)
Logic 0 Input Current (Leakage
Current)
Input Capacitance
7, 8
11
13
7
±50
20
±15
1
kΩ
μA
mA
μs
mV
μA
Each output has a common mode of 0.5 V × AV
DD
and swings 0.5 V × V
REF
above and below this;
V
REF
is the internal 2.5 V reference
Each output has a common mode of 0.5 V × V
REF
and swings 0.6 V × V
REF
above and below this;
V
REF
is the internal 2.5 V reference
Line driver buffer disabled
Line driver buffer disabled
No protection diodes, max allowable current
AGND
7
2
1
AV
DD
− 1.2 V
15
pF
mV
μs
Hysteresis can be turned on or off via the
CMPHYST bit in the CMPCON register
Response time can be modified via the CMPRES
bits in the CMPCON register
780
−1.3
±3
2.79
3.07
±2.5
50
0
512
10,000
20
±0.2
−40
−80
15
±1
−65
+125
mV
mV/°C
°C
V
V
%
μs
ms
sec
Cycles
Years
μA
μA
μA
pF
Two selectable trip points
Of the selected nominal trip point voltage
T
J
= 85°C
All digital inputs, including XCLKI and XCLKO
V
INH
= V
DD
or V
INH
= 5 V
V
INL
= 0 V, except TDI
V
INL
= 0 V, TDI Only
Rev. 0 | Page 5 of 92
