MicroConverter 12-Bit ADCs and DACs with
Embedded High Speed 62 kB Flash MCU
Data Sheet
FEATURES
Pin compatible upgrade of
ADuC812/ADuC831/ADuC832
Increased performance
Single-cycle 20 MIPS 8052 core
High speed 420 kSPS 12-bit ADC
Increased memory
Up to 62 kBytes on-chip Flash/EE program memory
4 kBytes on-chip Flash/EE data memory
In-circuit reprogrammable
Flash/EE, 100 year retention, 100 kCycle endurance
2304 bytes on-chip data RAM
Smaller package
8 mm × 8 mm chip scale package
52-lead PQFP—pin-compatible upgrade
Analog I/O
8-channel, 420 kSPS high accuracy, 12-bit ADC
On-chip, 15 ppm/°C voltage reference
DMA controller, high speed ADC-to-RAM capture
Two 12-bit voltage output DACs
1
Dual output PWM ∑-∆ DACs
On-chip temperature monitor function
8052 based core
8051 compatible instruction set (20 MHz max)
High performance single-cycle core
32 kHz external crystal, on-chip programmable PLL
12 interrupt sources, 2 priority levels
Dual data pointers, extended 11-bit stack pointer
On-chip peripherals
Time interval counter (TIC)
UART, I
2
C®, and SPI® Serial I/O
Watchdog timer (WDT)
Power supply monitor (PSM)
Power
Normal: 4.5 mA @ 3 V (core CLK = 2.098 MHz)
Power-down: 10 µA @ 3 V
2
Development tools
Low cost, comprehensive development system
incorporating nonintrusive single-pin emulation,
IDE based assembly and C source debugging
ADuC841/ADuC842/ADuC843
FUNCTIONAL BLOCK DIAGRAM
ADuC841/ADuC842/ADuC843
12-BIT
DAC
BUF
DAC
1
ADC0
ADC1
T/H
12-BIT ADC
12-BIT
DAC
BUF
DAC
1
MUX
ADC5
ADC6
ADC7
HARDWARE
CALIBRATON
TEMP
SENSOR
16-BIT
Σ-∆
DAC
16-BIT
Σ-∆
DAC
MUX
16-BIT
PWM
PWM1
PWM0
16-BIT
PWM
20 MIPS 8052 BASED MCU WITH ADDITIONAL
PERIPHERALS
PLL
2
62 kBYTES FLASH/EE PROGRAM MEMORY
4 kBYTES FLASH/EE DATA MEMORY
2304 BYTES USER RAM
3
×
16 BIT TIMERS
1
×
REAL TIME CLOCK
OSC
4
×
PARALLEL
PORTS
POWER SUPPLY MON
WATCHDOG TIMER
UART, I
2
C, AND SPI
SERIAL I/O
03260-0-001
INTERNAL
BAND GAP
VREF
CREF
XTAL1
XTAL2
Figure 1.
GENERAL DESCRIPTION
The
ADuC841/ADuC842/ADuC843
1
are complete smart
transducer front ends, that integrates a high performance self-
calibrating multichannel ADC, a dual DAC, and an optimized
single-cycle 20 MHz 8-bit MCU (8051 instruction set compatible)
on a single chip.
The
ADuC841
and
ADuC842
are identical with the exception
of the clock oscillator circuit; the
ADuC841
is clocked directly
from an external crystal up to 20 MHz whereas the
ADuC842
uses a 32 kHz crystal with an on-chip PLL generating a
programmable core clock up to 16.78 MHz.
The
ADuC843
is identical to the
ADuC842
except that the
ADuC843
has no analog DAC outputs.
The microcontroller is an optimized 8052 core offering up to
20 MIPS peak performance. Three different memory options
are available offering up to 62 kBytes of nonvolatile Flash/EE
program memory. Four kBytes of nonvolatile Flash/EE data
memory, 256 bytes RAM, and 2 kBytes of extended RAM are
also integrated on-chip.
1
APPLICATIONS
Optical networking—laser power control
Base station systems
Precision instrumentation, smart sensors
Transient capture systems
DAS and communications systems
ADuC841/ADuC842
only.
2
ADuC842/ADuC843
only,
ADuC841
driven directly by external crystal.
Rev. B
Document Feedback
1
Protected by U.S. Patent No. 5,969,657.
(continued
on page 23)
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2003–2017 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
ADuC841/ADuC842/ADuC843
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Absolute Maximum Ratings ............................................................ 8
ESD Caution .................................................................................. 8
Pin Configurations and Function Descriptions ........................... 9
Terminology .................................................................................... 19
ADC Specifications .................................................................... 19
DAC Specifications..................................................................... 19
Typical Performance Characteristics ........................................... 20
Functional Description .................................................................. 24
8052 Instruction Set ................................................................... 24
Other Single-Cycle Core Features ............................................ 26
Memory Organization ............................................................... 27
Special Function Registers (SFRs) ............................................ 28
Accumulator SFR (ACC) ........................................................... 29
Special Function Register Banks .............................................. 30
ADC Circuit Information.......................................................... 31
Calibrating the ADC .................................................................. 38
Nonvolatile Flash/EE Memory ................................................. 39
Using Flash/EE Data Memory .................................................. 42
Data Sheet
User Interface to On-Chip Peripherals.................................... 46
On-Chip PLL .............................................................................. 49
Pulse-Width Modulator (PWM) .............................................. 50
Serial Peripheral Interface (SPI) ............................................... 53
I
2
C Compatible Interface ........................................................... 56
Dual Data Pointer....................................................................... 59
Power Supply Monitor ............................................................... 60
Watchdog Timer ......................................................................... 61
Time Interval Counter (TIC) .................................................... 62
8052 Compatible On-Chip Peripherals ................................... 65
Timer/Counter 0 and 1 Operating Modes .............................. 70
Timer/Counter Operating Modes............................................ 72
UART Serial Interface ................................................................ 73
SBUF ............................................................................................ 73
Interrupt System ......................................................................... 78
Hardware Design Considerations ............................................ 80
Other Hardware Considerations .............................................. 84
Development Tools .................................................................... 85
QuickStart Development System ............................................. 85
Timing Specifications
, ,
.................................................................. 86
Outline Dimensions ....................................................................... 94
Ordering Guide .......................................................................... 95
REVISION HISTORY
6/2017—Rev. A to Rev. B
Change to Notes, Figure 4 ............................................................. 14
Changes to Figure 96 ...................................................................... 95
4/2016—Rev. 0 to Rev. A
Added Patent Note, Note 1 .............................................................. 1
Changes to Figure 3 and Table 3 ..................................................... 9
Changes to Figure 4 ........................................................................ 14
Added Table 4; Renumbered Sequentially .................................. 14
Changes to Using the DAC Section ............................................. 47
Updated Outline Dimensions ....................................................... 94
Changes to Ordering Guide .......................................................... 95
11/2003—Revision 0: Initial Version
Rev. B | Page 2 of 95
Data Sheet
SPECIFICATIONS
1
ADuC841/ADuC842/ADuC843
Table 1. AV
DD
= DV
DD
= 2.7 V to 3.6 V or 4.75 V to 5.25 V; V
REF
= 2.5 V internal reference, f
CORE
= 16.78 MHz @ 5 V 8.38 MHz @ 3 V;
all specifications T
A
= T
MIN
to T
MAX
, unless otherwise noted
Parameter
ADC CHANNEL SPECIFICATIONS
DC ACCURACY
2, 3
Resolution
Integral Nonlinearity
Differential Nonlinearity
Integral Nonlinearity
4
Differential Nonlinearity
4
Code Distribution
CALIBRATED ENDPOINT ERRORS
5, 6
Offset Error
Offset Error Match
Gain Error
Gain Error Match
DYNAMIC PERFORMANCE
Signal-to-Noise Ratio (SNR)
7
Total Harmonic Distortion (THD)
Peak Harmonic or Spurious Noise
Channel-to-Channel Crosstalk
8
ANALOG INPUT
Input Voltage Range
Leakage Current
Input Capacitance
TEMPERATURE SENSOR
9
Voltage Output at 25°C
Voltage TC
Accuracy
DAC CHANNEL SPECIFICATIONS
Internal Buffer Enabled
ADuC841/ADuC842
Only
DC ACCURACY
10
Resolution
Relative Accuracy
Differential Nonlinearity
11
Offset Error
Gain Error
Gain Error Mismatch
ANALOG OUTPUTS
Voltage Range_0
Voltage Range_1
Output Impedance
12
±3
–1
±1/2
±50
±1
±1
0.5
0 to V
REF
0 to V
DD
0.5
12
±3
–1
±1/2
±50
±1
±1
0.5
0 to V
REF
0 to V
DD
0.5
Bits
LSB typ
LSB max
LSB typ
mV max
% max
% typ
% typ
V typ
V typ
Ω typ
V
DD
= 5 V
V
DD
= 3 V
Unit
Test Conditions/Comments
f
SAMPLE
= 120 kHz, see the Typical
Performance Characteristics for typical
performance at other values of f
SAMPLE
12
±1
±0.3
+1/–0.9
±0.3
±2
+1.5/–0.9
1
±3
±1
±3
±1
12
±1
±0.3
+1/–0.9
±0.3
±1.5
+1.5/–0.9
1
±2
±1
±2
±1
Bits
LSB max
LSB typ
LSB max
LSB typ
LSB max
LSB max
LSB typ
LSB max
LSB typ
LSB max
LSB typ
f
IN
= 10 kHz sine wave
f
SAMPLE
= 120 kHz
71
–85
–85
–80
0 to V
REF
±1
32
700
–1.4
±1.5
71
–85
–85
–80
0 to V
REF
±1
32
700
–1.4
±1.5
dB typ
dB typ
dB typ
dB typ
V
µA max
pF typ
mV typ
mV/°C typ
°C typ
2.5 V internal reference
2.5 V internal reference
1 V external reference
1 V external reference
ADC input is a dc voltage
Internal/External 2.5 V V
REF
DAC load to AGND
R
L
= 10 kΩ, C
L
= 100 pF
Guaranteed 12-bit monotonic
V
REF
range
AV
DD
range
V
REF
range
% of full-scale on DAC1
DAC V
REF
= 2.5 V
DAC V
REF
= V
DD
Rev. B | Page 3 of 95
ADuC841/ADuC842/ADuC843
Parameter
DAC AC CHARACTERISTICS
Voltage Output Settling Time
Digital-to-Analog Glitch Energy
DAC CHANNEL SPECIFICATIONS
12, 13
Internal Buffer Disabled
ADuC841/ADuC842
Only
DC ACCURACY
10
Resolution
Relative Accuracy
Differential Nonlinearity
11
Offset Error
Gain Error
Gain Error Mismatch
4
ANALOG OUTPUTS
Voltage Range_0
REFERENCE INPUT/OUTPUT REFERENCE OUTPUT
14
Output Voltage (V
REF
)
Accuracy
Power Supply Rejection
Reference Temperature Coefficient
Internal V
REF
Power-On Time
EXTERNAL REFERENCE INPUT
15
Voltage Range (V
REF
)
4
Input Impedance
Input Leakage
POWER SUPPLY MONITOR (PSM)
DV
DD
Trip Point Selection Range
DV
DD
Power Supply Trip Point Accuracy
WATCHDOG TIMER (WDT)
4
Timeout Period
FLASH/EE MEMORY RELIABILITY CHARACTERISTICS
16
Endurance
17
Data Retention
18
DIGITAL INPUTS
Input Leakage Current (Port 0, EA)
Logic 1 Input Current
(All Digital Inputs), SDATA, SCLOCK
Logic 0 Input Current (Ports 1, 2, 3) SDATA, SCLOCK
Logic 1 to Logic 0 Transition Current (Ports 2 and 3)
RESET
V
DD
= 5 V
15
10
V
DD
= 3 V
15
10
Unit
µs typ
nV-sec typ
Data Sheet
Test Conditions/Comments
Full-scale settling time to within
½ LSB of final value
1 LSB change at major carry
12
±3
–1
±1/2
±5
±0.5
0.5
0 to V
REF
2.5
±10
65
±15
2
1
V
DD
20
1
12
±3
–1
±1/2
±5
±0.5
0.5
0 to V
REF
2.5
±10
67
±15
2
1
V
DD
20
1
Bits
LSB typ
LSB max
LSB typ
mV max
% typ
% typ
V typ
V
mV Max
dB typ
ppm/°C typ
ms typ
V min
V max
kΩ typ
µA max
Guaranteed 12-bit monotonic
V
REF
range
V
REF
range
% of full-scale on DAC1
DAC V
REF
= 2.5 V
Of V
REF
measured at the C
REF
pin
T
A
= 25°C
Internal band gap deselected via
ADCCON1.6
Two trip points selectable in this
range programmed via TPD1–0 in
PSMCON, 3 V part only
2.93
3.08
±2.5
0
2000
100,000
100
±10
±1
±10
±1
–75
–40
–660
–400
±10
10
105
0
2000
100,000
100
±10
±1
±10
±1
–25
–15
–250
–140
±10
5
35
V min
V max
% max
ms min
ms max
Cycles min
Years min
µA max
µA typ
µA max
µA typ
µA max
µA typ
µA max
µA typ
µA max
µA min
µA max
Nine timeout periods selectable in
this range
V
IN
= 0 V or V
DD
V
IN
= 0 V or V
DD
V
IN
= V
DD
V
IN
= V
DD
V
IL
= 450 mV
V
IL
= 2 V
V
IL
= 2 V
V
IN
= 0 V
V
IN
= 5 V, 3 V Internal Pull Down
V
IN
= 5 V, 3 V Internal Pull Down
Rev. B | Page 4 of 95
Data Sheet
Parameter
LOGIC INPUTS
4
INPUT VOLTAGES
All Inputs Except SCLOCK, SDATA, RESET, and
XTAL1
VINL, Input Low Voltage
VINH, Input High Voltage
SDATA
VINL, Input Low Voltage
VINH, Input High Voltage
SCLOCK and RESET ONLY
4
(Schmitt-Triggered Inputs)
V
T+
V
T–
V
T+
– V
T–
CRYSTAL OSCILLATOR
Logic Inputs, XTAL1 Only
V
INL
, Input Low Voltage
V
INH
, Input High Voltage
XTAL1 Input Capacitance
XTAL2 Output Capacitance
MCU CLOCK RATE
DIGITAL OUTPUTS
Output High Voltage (V
OH
)
V
DD
= 5 V
V
DD
= 3 V
Unit
ADuC841/ADuC842/ADuC843
Test Conditions/Comments
0.8
2.0
0.8
2.0
0.4
2.0
0.8
2.0
V max
V min
V max
V min
1.3
3.0
0.8
1.4
0.3
0.85
0.95
0.25
0.4
1.1
0.3
0.85
V min
V max
V min
V max
V min
V max
0.8
3.5
18
18
16.78
20
2.4
4
0.4
2.5
18
18
8.38
8.38
V typ
V typ
pF typ
pF typ
MHz max
MHz max
V min
V typ
V min
V typ
V max
V typ
V max
V max
µA max
µA typ
ms typ
µs typ
µs typ
µs typ
µs typ
ms typ
ms typ
ADuC842/ADuC843
Only
ADuC841
Only
V
DD
= 4.5 V to 5.5 V
I
SOURCE
= 80 µA
V
DD
= 2.7 V to 3.3 V
I
SOURCE
= 20 µA
I
SINK
= 1.6 mA
I
SINK
= 1.6 mA
I
SINK
= 4 mA
I
SINK
= 8 mA, I
2
C Enabled
2.4
2.6
Output Low Voltage (V
OL
)
ALE, Ports 0 and 2
Port 3
SCLOCK/SDATA
Floating State Leakage Current
4
STARTUP TIME
At Power-On
From Idle Mode
From Power-Down Mode
Wake-up with INT0 Interrupt
Wake-up with SPI/I
2
C Interrupt
Wake-up with External RESET
After External RESET in Normal Mode
After WDT Reset in Normal Mode
0.4
0.2
0.4
0.4
±10
±1
500
100
150
150
150
30
3
0.4
0.2
0.4
0.4
±10
±1
500
100
400
400
400
30
3
At any core CLK
Controlled via WDCON SFR
Rev. B | Page 5 of 95
