Changes to the Power Consumption Section .............................. 20
Changes to the Ordering Guide .................................................... 21
9/03—Rev. 0 to Rev. A
Edits to Regulatory Information ................................................... 13
Edits to Absolute Maximum Ratings ............................................ 15
Deleted the Package Branding Information ................................ 16
9/03—Revision 0: Initial Version
Rev. K | Page 3 of 32
ADuM1300/ADuM1301
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS—5 V, 105°C OPERATION
Data Sheet
All voltages are relative to their respective ground. 4.5 V ≤ V
DD1
≤ 5.5 V, 4.5 V ≤ V
DD2
≤ 5.5 V; all minimum/maximum specifications apply
over the entire recommended operation range, unless otherwise noted; all typical specifications are at T
A
= 25°C, V
DD1
= V
DD2
= 5 V. These
specifications do not apply to
ADuM1300W
and
ADuM1301W
automotive grade versions.
Table 1.
Parameter
DC SPECIFICATIONS
Input Supply Current per Channel, Quiescent
Output Supply Current per Channel, Quiescent
ADuM1300
Total Supply Current, Three Channels
1
DC to 2 Mbps
V
DD1
Supply Current
V
DD2
Supply Current
10 Mbps (BRW and CRW Grades Only)
V
DD1
Supply Current
V
DD2
Supply Current
90 Mbps (CRW Grade Only)
V
DD1
Supply Current
V
DD2
Supply Current
ADuM1301
Total Supply Current, Three Channels
1
DC to 2 Mbps
V
DD1
Supply Current
V
DD2
Supply Current
10 Mbps (BRW and CRW Grades Only)
V
DD1
Supply Current
V
DD2
Supply Current
90 Mbps (CRW Grade Only)
V
DD1
Supply Current
V
DD2
Supply Current
For All Models
Input Currents
Logic High Input Threshold
Logic Low Input Threshold
Logic High Output Voltages
Logic Low Output Voltages
Symbol
I
DDI (Q)
I
DDO (Q)
Min
Typ
0.50
0.19
Max Unit
0.53
0.24
mA
mA
Test Conditions
I
DD1 (Q)
I
DD2 (Q)
I
DD1 (10)
I
DD2 (10)
I
DD1 (90)
I
DD2 (90)
1.6
0.7
6.5
1.9
57
16
2.5
1.0
8.1
2.5
77
18
mA
mA
mA
mA
mA
mA
DC to 1 MHz logic signal freq.
DC to 1 MHz logic signal freq.
5 MHz logic signal freq.
5 MHz logic signal freq.
45 MHz logic signal freq.
45 MHz logic signal freq.
I
DD1 (Q)
I
DD2 (Q)
I
DD1 (10)
I
DD2 (10)
I
DD1 (90)
I
DD2 (90)
I
IA
, I
IB
, I
IC
, I
E1
, I
E2
V
IH
, V
EH
V
IL
, V
EL
V
OAH
, V
OBH
, V
OCH
V
OAL
, V
OBL
, V
OCL
−10
2.0
1.3
1.0
5.0
3.4
43
29
2.1
1.4
6.2
4.2
57
37
mA
mA
mA
mA
mA
mA
µA
V
V
V
V
V
V
V
DC to 1 MHz logic signal freq.
DC to 1 MHz logic signal freq.
5 MHz logic signal freq.
5 MHz logic signal freq.
45 MHz logic signal freq.
45 MHz logic signal freq.
0 V ≤ V
IA
, V
IB
, V
IC
≤ V
DD1
or V
DD2
,
0 V ≤ V
E1
, V
E2
≤ V
DD1
or V
DD2
+0.01 +10
0.8
(V
DD1
or V
DD2
) − 0.1
(V
DD1
or V
DD2
) − 0.4
5.0
4.8
0.0
0.04
0.2
0.1
0.1
0.4
I
Ox
= −20 µA, V
Ix
= V
IxH
I
Ox
= −4 mA, V
Ix
= V
IxH
I
Ox
= 20 µA, V
Ix
= V
IxL
I
Ox
= 400 µA, V
Ix
= V
IxL
I
Ox
= 4 mA, V
Ix
= V
IxL
SWITCHING SPECIFICATIONS
ADuM1300ARW/ADuM1301ARW
Minimum Pulse Width
2
Maximum Data Rate
3
Propagation Delay
4
Pulse Width Distortion, |t
PLH
− t
PHL
|
4
Change vs. Temperature
Propagation Delay Skew
5
Channel-to-Channel Matching
6
PW
t
PHL
, t
PLH
PWD
t
PSK
t
PSKCD
/t
PSKOD
1
50
65
11
1000 ns
Mbps
100 ns
40
ns
ps/°C
50
ns
50
ns
C
L
= 15 pF, CMOS signal levels
C
L
= 15 pF, CMOS signal levels
C
L
= 15 pF, CMOS signal levels
C
L
= 15 pF, CMOS signal levels
C
L
= 15 pF, CMOS signal levels
C
L
= 15 pF, CMOS signal levels
C
L
= 15 pF, CMOS signal levels
Rev. K | Page 4 of 32
Data Sheet
Parameter
ADuM1300BRW/ADuM1301BRW
Minimum Pulse Width
2
Maximum Data Rate
3
Propagation Delay
4
Pulse Width Distortion, |t
PLH
− t
PHL
|
4
Change vs. Temperature
Propagation Delay Skew
5
Channel-to-Channel Matching, Codirectional
Channels
6
Channel-to-Channel Matching, Opposing-
Directional Channels
6
ADuM1300CRW/ADuM1301CRW
Minimum Pulse Width
2
Maximum Data Rate
3
Propagation Delay
4
Pulse Width Distortion, |t
PLH
− t
PHL
|
4
Change vs. Temperature
Propagation Delay Skew
5
Channel-to-Channel Matching, Codirectional
Channels
6
Channel-to-Channel Matching, Opposing-
Directional Channels
6
For All Models
Output Disable Propagation Delay (High/Low
to High Impedance)
Output Enable Propagation Delay (High
Impedance to High/Low)
Output Rise/Fall Time (10% to 90%)
Common-Mode Transient Immunity at Logic
High Output
7
Common-Mode Transient Immunity at Logic
Low Output
7
Refresh Rate
Input Dynamic Supply Current per Channel
8
Output Dynamic Supply Current per Channel
8
1
ADuM1300/ADuM1301
Symbol
PW
t
PHL
, t
PLH
PWD
t
PSK
t
PSKCD
t
PSKOD
10
20
32
5
15
3
6
Min
Typ
Max Unit
100
50
3
ns
Mbps
ns
ns
ps/°C
ns
ns
ns
Test Conditions
C
L
= 15 pF, CMOS signal levels
C
L
= 15 pF, CMOS signal levels
C
L
= 15 pF, CMOS signal levels
C
L
= 15 pF, CMOS signal levels
C
L
= 15 pF, CMOS signal levels
C
L
= 15 pF, CMOS signal levels
C
L
= 15 pF, CMOS signal levels
C
L
= 15 pF, CMOS signal levels
PW
t
PHL
, t
PLH
PWD
t
PSK
t
PSKCD
t
PSKOD
90
18
8.3
120
27
0.5
3
11.1
32
2
10
2
5
ns
Mbps
ns
ns
ps/°C
ns
ns
ns
C
L
= 15 pF, CMOS signal levels
C
L
= 15 pF, CMOS signal levels
C
L
= 15 pF, CMOS signal levels
C
L
= 15 pF, CMOS signal levels
C
L
= 15 pF, CMOS signal levels
C
L
= 15 pF, CMOS signal levels
C
L
= 15 pF, CMOS signal levels
C
L
= 15 pF, CMOS signal levels
t
PHZ
, t
PLH
t
PZH
, t
PZL
t
R
/t
F
|CM
H
|
|CM
L
|
f
r
I
DDI (D)
I
DDO (D)
6
6
2.5
35
35
1.2
0.19
0.05
8
8
ns
ns
ns
kV/µs
kV/µs
Mbps
mA/Mbps
mA/Mbps
C
L
= 15 pF, CMOS signal levels
C
L
= 15 pF, CMOS signal levels
C
L
= 15 pF, CMOS signal levels
V
Ix
=
V
DD1
or V
DD2
, V
CM
= 1000 V,
transient magnitude = 800 V
V
Ix
= 0 V, V
CM
= 1000 V,
transient magnitude = 800 V
25
25
The supply current values are for all three channels combined when running at identical data rates. Output supply current values are specified with no output load
present. The supply current associated with an individual channel operating at a given data rate may be calculated as described in the Power Consumption section.
See Figure 6 through Figure 8 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See Figure 9 through
Figure 12 for total V
DD1
and V
DD2
supply currents as a function of data rate for
ADuM1300/ADuM1301
channel configurations.
2
The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed.
3
The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed.
4
t
PHL
propagation delay is measured from the 50% level of the falling edge of the V
Ix
signal to the 50% level of the falling edge of the V
Ox
signal. t
PLH
propagation delay is
measured from the 50% level of the rising edge of the V
Ix
signal to the 50% level of the rising edge of the V
Ox
signal.
5
t
PSK
is the magnitude of the worst-case difference in t
PHL
or t
PLH
that is measured between units at the same operating temperature, supply voltages, and output load
within the recommended operating conditions.
6
Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of
the isolation barrier. Opposing-directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with
inputs on opposing sides of the isolation barrier.
7
CM
H
is the maximum common-mode voltage slew rate that can be sustained while maintaining V
O
> 0.8 V
DD2
. CM
L
is the maximum common-mode voltage slew rate
that can be sustained while maintaining V
O
< 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient
magnitude is the range over which the common mode is slewed.
8
Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in signal data rate. See Figure 6 through Figure 8 for information
on per-channel supply current for unloaded and loaded conditions. See the Power Consumption section for guidance on calculating the per-channel supply current
