Changes to Ordering Guide .......................................................... 20
3/06—Rev. C to Rev. D
Added Note 1 and Changes to Figure 2 ..........................................1
Changes to Absolute Maximum Ratings ..................................... 11
11/05—Rev. SpB to Rev. C: Initial Version
Rev. H | Page 2 of 24
ADuM1410/ADuM1411/ADuM1412
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS—5 V OPERATION
4.5 V ≤ V
DD1
≤ 5.5 V, 4.5 V ≤ V
DD2
≤ 5.5 V; all minimum/maximum specifications apply over the entire recommended operation range,
unless otherwise noted; all typical specifications are at T
A
= 25°C, V
DD1
= V
DD2
= 5 V. All voltages are relative to their respective ground.
Table 1.
Parameter
DC SPECIFICATIONS
Input Supply Current per Channel,
Quiescent
Output Supply Current per Channel,
Quiescent
ADuM1410, Total Supply Current,
Four Channels
1
DC to 2 Mbps
V
DD1
Supply Current
V
DD2
Supply Current
10 Mbps (BRWZ Version Only)
V
DD1
Supply Current
V
DD2
Supply Current
ADuM1411, Total Supply Current,
Four Channels
1
DC to 2 Mbps
V
DD1
Supply Current
V
DD2
Supply Current
10 Mbps (BRWZ Version Only)
V
DD1
Supply Current
V
DD2
Supply Current
ADuM1412, Total Supply Current,
Four Channels
1
DC to 2 Mbps
V
DD1
or V
DD2
Supply Current
10 Mbps (BRWZ Version Only)
V
DD1
or V
DD2
Supply Current
All Models
Input Currents
Symbol
I
DDI (Q)
I
DDO (Q)
Min
Typ
0.50
0.38
Max
0.73
0.53
Unit
mA
mA
Test Conditions
I
DD1 (Q)
I
DD2 (Q)
I
DD1 (10)
I
DD2 (10)
2.4
1.2
8.8
2.8
3.2
1.6
12
4.0
mA
mA
mA
mA
DC to 1 MHz logic signal frequency
DC to 1 MHz logic signal frequency
5 MHz logic signal frequency
5 MHz logic signal frequency
I
DD1 (Q)
I
DD2 (Q)
2.2
1.8
2.8
2.4
mA
mA
DC to 1 MHz logic signal
frequency
DC to 1 MHz logic signal
frequency
5 MHz logic signal frequency
5 MHz logic signal frequency
I
DD1 (10)
I
DD2 (10)
5.4
3.8
7.6
5.3
mA
mA
I
DD1 (Q)
, I
DD2 (Q)
2.0
2.6
mA
DC to 1 MHz logic signal
frequency
5 MHz logic signal frequency
0 V ≤ V
IA
, V
IB
, V
IC
, V
ID
≤ V
DD1
or V
DD2
,
0 V ≤ V
CTRL1
, V
CTRL2
≤ V
DD1
or V
DD2
,
0 V ≤ V
DISABLE
≤ V
DD1
I
DD1 (10)
, I
DD2 (10)
I
IA
, I
IB
, I
IC
,
I
ID
, I
CTRL1
,
I
CTRL2
, I
DISABLE
V
IH
V
IL
V
OAH
, V
OBH
,
V
OCH
, V
ODH
V
OAL
, V
OBL
,
V
OCL
, V
ODL
−10
4.6
+0.01
6.5
+10
mA
μA
Logic High Input Threshold
Logic Low Input Threshold
Logic High Output Voltages
Logic Low Output Voltages
2.0
0.8
(V
DD1
or V
DD2
) − 0.1
(V
DD1
or V
DD2
) − 0.4
5.0
4.8
0.0
0.04
0.2
0.1
0.1
0.4
V
V
V
V
V
V
V
I
Ox
= −20 μA, V
Ix
= V
IxH
I
Ox
= −4 mA, V
Ix
= V
IxH
I
Ox
= 20 μA, V
Ix
= V
IxL
I
Ox
= 400 μA, V
Ix
= V
IxL
I
Ox
= 4 mA, V
Ix
= V
IxL
Rev. H | Page 3 of 24
ADuM1410/ADuM1411/ADuM1412
Parameter
SWITCHING SPECIFICATIONS
ADuM141xARWZ
Minimum Pulse Width
2
Maximum Data Rate
3
Propagation Delay
4
Pulse Width Distortion, |t
PLH
− t
PHL
|
4
Propagation Delay Skew
5
Channel-to-Channel Matching
6
ADuM141xBRWZ
Minimum Pulse Width
2
Maximum Data Rate
3
Propagation Delay
4
Pulse Width Distortion, |t
PLH
− t
PHL
|
4
Change vs. Temperature
Propagation Delay Skew
5
Channel-to-Channel Matching,
Codirectional Channels
6
Channel-to-Channel Matching,
Opposing-Directional Channels
6
All Models
Output Rise/Fall Time (10% to 90%)
Common-Mode Transient Immunity
at Logic High Output
7
Common-Mode Transient Immunity
at Logic Low Output
7
Refresh Rate
Input Enable Time
8
Input Disable Time
8
Input Dynamic Supply Current
per Channel
9
Output Dynamic Supply Current
per Channel
9
1
Symbol
Min
Typ
Max
Unit
Test Conditions
PW
t
PHL
, t
PLH
PWD
t
PSK
t
PSKCD/OD
PW
t
PHL
, t
PLH
PWD
t
PSK
t
PSKCD
t
PSKOD
10
20
30
5
1
20
65
1000
100
40
50
50
100
50
5
30
5
6
ns
Mbps
ns
ns
ns
ns
ns
Mbps
ns
ns
ps/°C
ns
ns
ns
C
L
= 15 pF, CMOS signal levels
C
L
= 15 pF, CMOS signal levels
C
L
= 15 pF, CMOS signal levels
C
L
= 15 pF, CMOS signal levels
C
L
= 15 pF, CMOS signal levels
C
L
= 15 pF, CMOS signal levels
C
L
= 15 pF, CMOS signal levels
C
L
= 15 pF, CMOS signal levels
C
L
= 15 pF, CMOS signal levels
C
L
= 15 pF, CMOS signal levels
C
L
= 15 pF, CMOS signal levels
C
L
= 15 pF, CMOS signal levels
C
L
= 15 pF, CMOS signal levels
C
L
= 15 pF, CMOS signal levels
t
R
/t
F
|CM
H
|
|CM
L
|
f
r
t
ENABLE
t
DISABLE
I
DDI (D)
I
DDO (D)
25
25
2.5
35
35
1.2
2.0
5.0
0.12
0.04
ns
kV/μs
kV/μs
Mbps
μs
μs
mA/
Mbps
mA/
Mbps
C
L
= 15 pF, CMOS signal levels
V
Ix
= V
DD1
or V
DD2
, V
CM
= 1000 V,
transient magnitude = 800 V
V
Ix
= 0 V, V
CM
= 1000 V,
transient magnitude = 800 V
V
IA
, V
IB
, V
IC
, V
ID
= 0 V or V
DD1
V
IA
, V
IB
, V
IC
, V
ID
= 0 V or V
DD1
The supply current values for all four channels are combined when running at identical data rates. Output supply current values are specified with no output load
present. The supply current associated with an individual channel operating at a given data rate can be calculated as described in the Power Consumption section.
See Figure 8 through Figure 10 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See Figure 11 through
Figure 15 for total V
DD1
and V
DD2
supply currents as a function of data rate for ADuM1410/ADuM1411/ADuM1412 channel configurations.
2
The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed.
3
The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed.
4
t
PHL
propagation delay is measured from the 50% level of the falling edge of the V
Ix
signal to the 50% level of the falling edge of the V
Ox
signal. t
PLH
propagation delay is
measured from the 50% level of the rising edge of the V
Ix
signal to the 50% level of the rising edge of the V
Ox
signal.
5
t
PSK
is the magnitude of the worst-case difference in t
PHL
or t
PLH
that is measured between units at the same operating temperature, supply voltages, and output load
within the recommended operating conditions.
6
Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of
the isolation barrier. Opposing-directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with
inputs on opposing sides of the isolation barrier.
7
|CM
H
| is the maximum common-mode voltage slew rate that can be sustained while maintaining V
O
> 0.8 V
DD2
. |CM
L
| is the maximum common-mode voltage slew rate
that can be sustained while maintaining V
O
< 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient
magnitude is the range over which the common mode is slewed.
8
Input enable time is the duration from when V
DISABLE
is set low until the output states are guaranteed to match the input states in the absence of any input data logic
transitions. If an input data logic transition within a given channel does occur within this time interval, the output of that channel reaches the correct state within the
much shorter duration as determined by the propagation delay specifications within this data sheet. Input disable time is the duration from when V
DISABLE
is set high
until the output states are guaranteed to reach their programmed output levels, as determined by the CTRL
2
logic state (see Table 14).
9
Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in signal data rate. See Figure 8 through Figure 10 for information
on per-channel supply current for unloaded and loaded conditions. See the Power Consumption section for guidance on calculating the per-channel supply current
for a given data rate.
Rev. H | Page 4 of 24
ADuM1410/ADuM1411/ADuM1412
ELECTRICAL CHARACTERISTICS—3 V OPERATION
2.7 V ≤ V
DD1
≤ 3.6 V, 2.7 V ≤ V
DD2
≤ 3.6 V; all minimum/maximum specifications apply over the entire recommended operation range,
unless otherwise noted; all typical specifications are at T
A
= 25°C, V
DD1
= V
DD2
= 3.0 V. All voltages are relative to their respective ground.
