300 MHz, 32 × 16 Buffered
Analog Crosspoint Switch
ADV3202/ADV3203
FEATURES
Large, 32 × 16, nonblocking switch array
G = +1 (ADV3202) or G = +2 (ADV3203) operation
32 × 32 pin-compatible version available (ADV3200/ADV3201)
Single +5 V, dual ±2.5 V, or dual ±3.3 V supply (G = +2)
Serial programming of switch array
2:1 OSD insertion mux per output
Input sync-tip clamp
High impedance output disable allows connection of
multiple devices with minimal output bus load
Excellent video performance
60 MHz 0.1 dB gain flatness
0.1% differential gain error (R
L
= 150 Ω)
0.1° differential phase error (R
L
= 150 Ω)
Excellent ac performance
Bandwidth: >300 MHz
Slew rate: >400 V/μs
Low power: 1 W
Low all hostile crosstalk: −48 dB @ 5 MHz
Reset pin allows disabling of all outputs
Connected through a capacitor to ground, provides
power-on reset capability
176-lead exposed pad LQFP package (24 mm × 24 mm)
CLK
193-BIT SHIFT REGISTER
DATA IN
97
UPDATE
CS
RESET
ENABLE/
BYPASS
SYNC-TIP
CLAMP
PARALLEL LATCH
96
16 × 5:32
DECODERS
96
DATA
OUT
FUNCTIONAL BLOCK DIAGRAM
VPOS VNEG DVCC DGND
ADV3202
(ADV3203)
16
ENABLE/
DISABLE
512
OUTPUT
BUFFER
G = +1
(G = +2)
32
INPUTS
.
.
.
.
.
.
SWITCH
MATRIX
OSD
MUX
.
.
.
.
.
.
16
OUTPUTS
16
REFERENCE
16
APPLICATIONS
CCTV surveillance
Routing of high speed signals, including
Composite video (NTSC, PAL, S, SECAM)
RGB and component video routing
Compressed video (MPEG, wavelet)
Video conferencing
VCLAMP
OSD
OSD
VREF
INPUTS SWITCHES
07526-001
Figure 1.
GENERAL DESCRIPTION
The ADV3202/ADV3203 are 32 × 16 analog crosspoint switch
matrices. They feature a selectable sync-tip clamp input for
ac-coupled applications and a 2:1 on-screen display (OSD)
insertion mux. With −48 dB of crosstalk and −80 dB isolation
at 5 MHz, the ADV3202/ADV3203 are useful in many high
density routing applications. The 0.1 dB flatness out to 60 MHz
makes the ADV3202/ADV3203 ideal for both composite and
component video switching.
The 16 independent output buffers of the ADV3202/ADV3203
can be placed into a high impedance state for paralleling cross-
point outputs so that off-channels present minimal loading to
an output bus if building a larger array. The ADV3202 has a
gain of +1 while the ADV3203 has a gain of +2 for ease of use in
back-terminated load applications. A single +5 V supply, dual
±2.5 V supplies, or dual ±3.3 V supplies (G = +2) can be used
while consuming only 195 mA of idle current with all outputs
enabled. The channel switching is performed via a double
buffered, serial digital control that can accommodate daisy
chaining of several devices.
The ADV3202/ADV3203 are packaged in a 176-lead exposed
pad LQFP package (24 mm× 24 mm) and are available over the
extended industrial temperature range of −40°C to +85°C.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2008 Analog Devices, Inc. All rights reserved.
ADV3202/ADV3203
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
OSD Disabled ................................................................................ 3
OSD Enabled ................................................................................. 4
Timing Characteristics (Serial Mode) ....................................... 5
Absolute Maximum Ratings............................................................ 6
Thermal Resistance ...................................................................... 6
Power Dissipation..........................................................................6
ESD Caution...................................................................................6
Pin Configuration and Function Descriptions..............................7
Truth Table and Logic Diagram ............................................... 10
Typical Performance Characteristics ........................................... 11
Theory of Operation ...................................................................... 14
Applications Information .............................................................. 16
Programming .............................................................................. 16
Outline Dimensions ....................................................................... 17
Ordering Guide .......................................................................... 17
REVISION HISTORY
10/08—Revision 0: Initial Version
Rev. 0 | Page 2 of 20
ADV3202/ADV3203
SPECIFICATIONS
OSD DISABLED
V
S
= ±2.5 V (ADV3202), V
S
= ±3.3 V (ADV3203) at T
A
= 25°C, G = +1 (ADV3202), G = +2 (ADV3203), R
L
= 150 Ω, all configurations,
unless otherwise noted.
Table 1.
Parameter
DYNAMIC PERFORMANCE
−3 dB Bandwidth
Gain Flatness
Settling Time
Slew Rate
NOISE/DISTORTION PERFORMANCE
Differential Gain Error
Differential Phase Error
Crosstalk, All Hostile, RTI
Conditions
200 mV p-p
2 V p-p
0.1 dB, 200 mV p-p
0.1 dB, 2 V p-p
1% , 2 V step
2 V step, peak
NTSC or PAL
NTSC or PAL
f = 5 MHz, R
L
= 150 Ω
R
L
= 1 kΩ
f = 100 MHz, R
L
= 150 Ω
R
L
= 1 kΩ
f = 5 MHz, one channel
0.1 MHz to 50 MHz
Broadcast mode, no load
Broadcast mode
No load, channel-to-channel
Channel-to-channel
DC, enabled
DC, disabled
Disabled
ADV3202
ADV3203
ADV3203, no output load
Min
ADV3202/ADV3203
Typ
Max
300
120
60
40
6
400
0.06/0.1
0.06/0.03
−48
−65
−23
−30
−80
25/22
±0.5
±0.5
±0.5/±0.8
±0.5/±0.8
0.15
1000/4
3.7
−1.2 to +1.2
−1.6 to +2.0
−2.0 to +2.0
±5
−1.2 to +1.2
−0.8 to +1.0
−1.0 to +1.0
3
4
3
−1
−3
50
40
300
±30
±1.75/±2.2
±2.2/±2.7
±2.8
±3.4
Unit
MHz
MHz
MHz
MHz
ns
V/μs
%
Degrees
dB
dB
dB
dB
dB
nV/√Hz
%
%
%
%
Ω
kΩ
pF
V
V
V
mV
V
V
V
pF
MΩ
μA
mA
μA
ns
ns
mV p-p
Off Isolation, Input-to-Output
Input Voltage Noise
DC PERFORMANCE
Gain Error
Gain Matching
OUTPUT CHARACTERISTICS
Output Impedance
Output Capacitance
Output Voltage Range
900/3.2
−1.1 to +1.1
−1.5 to +1.5
−1.5 to +1.5
INPUT CHARACTERISTICS
Input Offset Voltage
Input Voltage Range
ADV3202
ADV3203
ADV3203, no output load
−1.1 to +1.1
−0.75 to +0.75
−0.75 to +0.75
1
0.1
−2.9
−10
Input Capacitance
Input Resistance
Input Bias Current
Sync-tip clamp enabled,
V
IN
= VCLAMP + 0.1 V
Sync-tip clamp enabled,
V
IN
= VCLAMP − 0.1 V
Sync-tip clamp disabled
50% update to 1% settling
50% update to 1% settling
IN00 to IN31, RTI
12
−0.25
SWITCHING CHARACTERISTICS
Enable On Time
Switching Time, 2 V Step
Switching Transient (Glitch)
Rev. 0 | Page 3 of 20
ADV3202/ADV3203
Parameter
POWER SUPPLIES
Supply Current
Conditions
V
POS
or V
NEG
, outputs enabled,
no load
V
POS
or V
NEG
, outputs disabled
D
VCC
V
POS
− V
NEG
V
NEG
, V
POS
, f = 1 MHz
Operating (still air)
Operating (still air)
Min
ADV3202/ADV3203
Typ
Max
195/200
120/130
2.5
5 ± 10%/
6.6 ± 10%
−50/−45
−40 to +85
16
220/235
155/165
3.5
Unit
mA
mA
mA
V
dB
°C
°C/W
Supply Voltage Range
PSR
OPERATING TEMPERATURE RANGE
Temperature Range
θ
JA
OSD ENABLED
V
S
= ±2.5 V (ADV3202), V
S
= ±3.3 V (ADV3203) at T
A
= 25°C, G = +1 (ADV3202), G = +2 (ADV3203), R
L
= 150 Ω, all configurations,
unless otherwise noted.
Table 2.
Parameter
OSD DYNAMIC PERFORMANCE
−3 dB Bandwidth
Gain Flatness
Settling Time
Slew Rate
OSD NOISE/DISTORTION PERFORMANCE
Differential Gain Error
Differential Phase Error
Input Voltage Noise
OSD DC PERFORMANCE
Gain Error
OSD INPUT CHARACTERISTICS
Input Bias Current
OSD SWITCHING CHARACTERISTICS
OSD Switch Delay, 2 V Step
OSD Switching Transient (Glitch)
Conditions
200 mV p-p
2 V p-p
0.1 dB, 200 mV p-p
0.1 dB, 2 V p-p
1%, 2 V step
2 V step, peak
NTSC or PAL
NTSC or PAL
0.5 MHz to 50 MHz
No load
Min
ADV3202/ADV3203
Typ
Max
170/150
135/130
35
35
6
400
0.12/0.35
0.06/0.04
27/25
±0.1
±0.1
−10
−4
20
15/40
±2.3/±2.2
±2.7
Unit
MHz
MHz
MHz
MHz
ns
V/μs
%
Degrees
nV/√Hz
%
%
μA
ns
mV p-p
Sync-tip clamp disabled
50% OSD switch to 1% settling
Rev. 0 | Page 4 of 20
ADV3202/ADV3203
TIMING CHARACTERISTICS (SERIAL MODE)
Specifications subject to change without notice.
Table 3.
Parameter
Serial Data Setup Time
CLK Pulse Width
Serial Data Hold Time
CLK Pulse Separation
CLK to UPDATE Delay
UPDATE Pulse Width
CLK to DATA OUT Valid
Propagation Delay, UPDATE to Switch On or Off
Data Load Time, CLK = 5 MHz, Serial Mode
RESET Time
Symbol
t
1
t
2
t
3
t
4
t
5
t
6
t
7
Min
40
50
50
150
40
130
50
38.6
160
Limit
Typ
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
μs
ns
50
160
1
CS
0
1
CLK
0
t
2
t
4
LOAD DATA INTO
SERIAL REGISTER
ON RISING EDGE
t
1
1
DATA IN
0
1 = LATCHED
UPDATE
0 = TRANSPARENT
t
3
OUT15 (D5)
OUT00 (D0)
CLAMP
ON/OFF
t
5
TRANSFER DATA FROM SERIAL
REGISTER TO PARALLEL
LATCHES DURING LOW LEVEL
t
6
t
7
DATA OUT
07526-002
Figure 2. Timing Diagram, Serial Mode
Table 4. Logic Levels, DVCC = 3.3 V
V
IH
RESET, CS,
CLK, DATA IN,
UPDATE, OSDS
2.5 V min
V
IL
RESET, CS,
CLK, DATA IN,
UPDATE, OSDS
0.8 V max
V
OH
DATA OUT
V
OL
DATA OUT
I
IH
RESET, CS,
CLK, DATA IN,
UPDATE, OSDS
0.5 μA typ
I
IL
RESET, CS,
CLK, DATA IN,
UPDATE, OSDS
−0.5 μA typ
I
OH
DATA OUT
I
OL
DATA OUT
2.7 V min
0.5 V max
3 mA typ
−3 mA typ
Rev. 0 | Page 5 of 20
DSP 与 ARM 处理器
