a
FEATURES
Four 10-Bit Video DACs (4:2:2, YCrCb, RGB I/P
Supported)
10-Bit Video Rate Digitization at up to 54 MHz
AGC Control ( 6 dB)
Front End 3-Channel Clamp Control
Up to Five CVBS Input Channels, Two Component YUV,
Three S-Video, or a Combination of the Above. Simul-
taneous Digitization of Two CVBS Input Channels
Aux 8-Bit SAR ADC @ 843 kHz Sampling Giving up to
Eight General-Purpose Inputs
2
I C Compatible Interface with I
2
C Filter
RGB Inputs for Picture-on-Picture of the RGB DACs
Optional Internal Reference
Power Save Mode
APPLICATIONS
Picture-on-Picture Video Systems
Simultaneous Video Rate Processing
Hybrid Set-Top Box TV Systems
Direct Digital Synthesis/I-Q Demodulation
Image Processing
Simultaneous Sampling
Video Rate Codec
ADV7202
GENERAL DESCRIPTION
The ADV7202 is a video rate sampling codec.
It has the capability of sampling up to five NTSC/PAL/SECAM
video I/P signals. The resolution on the front end digitizer is
12 bits; 2 bits (12 dB) are used for gain and offset adjustment.
The digitizer has a conversion rate of up to 54 MHz.
The ADV7202 can have up to eight auxiliary inputs that can be
sampled by an 843 kHz SAR ADC for system monitoring.
The back end consists of four 10-bit DACs that run at up to
200 MHz and can be used to output CVBS, S-Video, Component
YCrCb, and RGB.
This codec also supports Picture-on-Picture.
The ADV7202 can operate at 3.3 V or 5 V. Its monolithic CMOS
construction ensures greater functionality with lower power
dissipation.
The ADV7202 is packaged in a small 64-lead LQFP package.
FUNCTIONAL BLOCK DIAGRAM
XTAL
DOUT DAC_DATA
[9:0]
[9:0]
OSD I/P “S”
AIN1P
AIN1M
AIN2P
AIN2M
AIN3P
AIN3M
AIN4P
AIN4M
AIN5P
AIN5M
AIN6P
AIN6M
I/P
I/P
MUX
SHA AND
CLAMP
SHA AND
CLAMP
SHA AND
CLAMP
MUX
ADC BLOCK
12-BIT
12-BIT
A/D
A/D
10-BIT
D/A
DAC0
10-BIT
D/A
ADC
LOGIC
A/D
A/D
DAC
LOGIC
10-BIT
8-BIT 843kHz
D/A
DAC2
DAC1
10-BIT
D/A
DAC3
ADV7202
I
2
C
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2002
ADV7202–SPECIFICATIONS
5 V SPECIFICATIONS
(AVDD/DVDD = 5 V
Parameter
STATIC PERFORMANCE_DAC
Resolution (Each DAC)
Accuracy (Each DAC)
Integral Nonlinearity
Differential Nonlinearity
VIDEO ADC
Resolution
Accuracy
Integral Nonlinearity
Differential Nonlinearity
Input Voltage Range
2
SNR
AUX ADC
Resolution
Differential Nonlinearity
Integral Nonlinearity
Input Voltage Range
DIGITAL INPUTS
Input High Voltage, V
INH
Input Low Voltage, V
INL
Input Leakage Current, I
IN
Input Capacitance, C
IN
DIGITAL OUTPUTS
Output High Voltage, V
OH
Output Low Voltage, V
OL
Three-State Leakage Current
Output Capacitance
Digital Output Access Time, t
14
Digital Output Hold Time, t
15
ANALOG OUTPUTS
Output Current Range
DAC-to-DAC Matching
Output Compliance, V
OC
Output Impedance, R
OUT
Output Capacitance, C
OUT
Analog Output Delay
3
DAC Output Skew
VOLTAGE REFERENCE
Reference Range, V
REFDAC
Reference Range, V
REFADC
Reference Range, V
REFADC
Min
5%, V
REF
= 1.235 V, R
SET
= 1.2 k , all specifications T
MIN
to T
MAX1
, unless otherwise noted.)
Typ
10
10
±
0.6
–0.6/0.1
12
12
±
2.5
±
0.7
Max
Unit
Bits
Bits
LSB
LSB
Bits
Bits
LSB
LSB
+V
REFADC
62
57
8
±
0.4
±
0.4
dB
dB
Bits
LSB
LSB
V
V
V
µA
pF
V
V
µA
pF
ns
ns
mA
%
V
kΩ
pF
ns
ns
V
V
V
I
SOURCE
= 400
µA
I
SINK
= 1.6 mA
See Figure 13
27 MHz Clock
54 MHz Clock
Test Conditions
–1.5
+0.5
10-Bit Operation
10-Bit Operation
(Including 2 Bits for Gain Ranging)
2.2 V Ref.
12 Bit
12 Bit
–V
REFADC
Guaranteed No Missing Codes
0
2
2 V
REFADC
0.8
±
2
6
2.4
0.4
10
10
6
5
4.10
0
50
30
5.5
0.06
1.17
2.1
1.235
2.2
1.1
1.30
2.30
4.33
3
4.6
1.4
R
SET
= 1.2 kΩ, R
L
= 300
Ω
I
OUT
= 0 mA
Programmable 1.1 V or 2.2 V
NOTES
1
0°C to 70°C.
2
SHA gain = 1, half range for SHA gain = 2, see Table II.
3
Output delay measured from 50% of the rising edge of the clock to the 50% point of full-scale transition.
Specifications subject to change without notice.
–2–
REV. 0
ADV7202
5 V SPECIFICATIONS
Parameter
POWER REQUIREMENTS
1
AVDD/DVDD
Normal Power Mode
I
DAC2
I
DSC3
I
ADC4
I
ADC4
Sleep Mode Current
5
Power-Up Time
MPU PORT
6
—I
2
C
SCLOCK Frequency
SCLOCK High Pulsewidth, t
1
SCLOCK Low Pulsewidth, t
2
Hold Time (Start Condition), t
3
Setup Time (Start Condition), t
4
Data Setup Time, t
5
SDATA, SCLOCK Rise Time, t
6
SDATA, SCLOCK Fall Time, t
7
Setup Time (Stop Condition), t
8
NOTES
1
All DACs and ADCs on.
2
I
DAC
is the DAC supply current.
3
I
DSC
is the digital core supply current.
4
I
ADC
is the ADC supply current.
5
This includes I
ADC
, I
DAC
, and I
DSC
.
6
Guaranteed by characterization.
Specifications subject to change without notice.
(AVDD/DVDD = 5 V
Min
4.75
5%, V
REF
= 1.235 V, R
SET
= 1.2 k , all specifications T
MIN
to T
MAX
, unless otherwise noted.)
Typ
5
Max
5.25
22
12
115
Unit
V
mA
mA
mA
mA
µA
ms
kHz
µs
µs
µs
µs
ns
ns
ns
µs
R
SET
= 1.2 kΩ, R
L
= 300
Ω
Inputs at Supply
Max Power YUV Mode
CVBS Input Mode
Internal Reference
Test Conditions
95
65
400
4
0
0.6
1.3
0.6
0.6
100
400
After this period the first clock is
generated.
Relevant for Repeated Start Condition
300
300
0.6
REV. 0
–3–
ADV7202–SPECIFICATIONS
5 V SPECIFICATIONS
(AVDD/DVDD = 4.75 V – 5.25 V, V
Parameter
PROGRAMMABLE GAIN
AMPLIFIER
Video ADC Gain
CLAMP CIRCUITRY
3
Clamp Fine Source/Sink Current
Clamp Coarse Source/Sink Current
CLOCK CONTROL
4
DACCLK0/DACCLK1
DACCLK1
5, 6, 7
DACCLK1
Data Setup Time, t
127
Data Hold Time, t
137
Min Clock High Time, t
107
Min Clock Low Time, t
117
Pipeline Delay
8
Video ADC
RESET CONTROL
RESET
Low Time
Min
Typ
REF
= 1.235 V, R
SET
= 1.2 k
, all specifications T
MIN
to T
MAX1
, unless otherwise noted.)
Condition
2
Max
Unit
–6
4.0
0.8
27
+6
dB
µA
mA
MHz
MHz
MHz
ns
ns
ns
ns
Clock Cycles
ns
Setup Conditions
200
27
1.5
1.5
1.5
1.5
4
10
Dual CLK Dual Edge Mode
Single Edge Single Clock Mode
4:2:2 Mode
All Input Modes
NOTES
1
Temperature range T
MIN
to T
MAX
: 0
o
C to 70
o
C.
2
The max/min specifications are guaranteed over this range. The max/min values are typical over 4.75 V to 5.25 V range.
3
External clamp capacitor = 0.1
µF.
4
TTL input values are 0 V to 3 V, with input rise/fall times
≤3
ns, measured between the 10% and 90% points. Timing reference points at 50% for inputs and outputs.
Analog output load
≤10
pF.
5
Maximum clock speed determined by setup and hold conditions.
6
Single DAC only.
7
Guaranteed by characterization.
8
Output delay measured from the 50% point of the rising edge of CLOCK to the 50% point of full-scale transition.
Specifications subject to change without notice.
–4–
REV. 0
ADV7202
3.3 V SPECIFICATIONS
Parameter
STATIC PERFORMANCE_DAC
Resolution (Each DAC)
Accuracy (Each DAC)
Integral Nonlinearity
Differential Nonlinearity
VIDEO ADC
Resolution
Accuracy
Integral Nonlinearity
Differential Nonlinearity
Differential Input Voltage Range
2
SNR
AUX ADC
Resolution
Differential Nonlinearity
Integral Nonlinearity
Input Voltage Range
DIGITAL INPUTS
Input High Voltage, V
INH
Input Low Voltage, V
INL
Input Current, I
IN
Input Capacitance, C
IN
DIGITAL OUTPUTS
Output High Voltage, V
OH
Output Low Voltage, V
OL
Three-State Leakage Current
Output Capacitance
Digital Output Access Time, t
14
Digital Output Hold Time, t
15
ANALOG OUTPUTS
Output Current
DAC-to-DAC Matching
Output Compliance, V
OC
Output Impedance, R
OUT
Output Capacitance, C
OUT
Analog Output Delay
3
DAC Output Skew
VOLTAGE REFERENCE
Reference Range, V
REFADC
Reference Range, V
REFDAC
(AVDD/DVDD = 3.3 V
Min
5%, V
REF
= 1.235 V, R
SET
= 1.2 k , all specifications T
MIN
to T
MAX1
, unless otherwise noted.)
Typ
10
10
±
1
–0.8/0.1
12
12
±
4
±
1
Max
Unit
Bits
Bits
LSB
LSB
Bits
Bits
LSB
LSB
+V
REFADC
60
55
8
±
0.5
±
0.5
dB
dB
Bits
LSB
LSB
V
V
V
µA
pF
V
V
µA
pF
ns
ns
mA
%
V
kΩ
pF
ns
ns
V
V
I
SOURCE
= 400
µA
I
SINK
= 1.6 mA
See Figure 13
Test Conditions
10-Bit Operation
10-Bit Operation
(Including 2 Bits for Gain Ranging)
2.2 V Ref.
12 Bit
12 Bit
See Table II
27 MHz Clock, f
IN
= 100 kHz
54 MHz Clock
–V
REFADC
0
2
2 V
REFADC
0.8
±
1
10
2.4
0.4
10
10
6
5
4.33
4
0
50
30
5.5
0.06
1.100
1.235
1.4
R
SET
= 1.2 kΩ, R
L
= 300
Ω
DAC 0, 1, and 2
I
OUT
= 0 mA
NOTES
1
0°C to 70°C.
2
SHA gain = 1, half range for SHA gain = 2, see Table II.
3
Output delay measured from 50% of the rising edge of the clock to the 50% point of full-scale transition.
Specifications subject to change without notice.
REV. 0
–5–
