AFBR-5972Z
Compact 650nm Transceiver with Compact Versatile-Link
connector for Fast Ethernet over POF
Data Sheet
Description
The AFBR-5972Z Transceiver provides the system designer
with the ability to implement Fast Ethernet (100 Mbps)
over standard bandwidth 0.5±0.05 NA POF. It features a
very compact design and has a form factor similar to the
UTP connector. This transceiver features a new compact
Versatile-Link duplex connector AFBR-4526Z and is com-
patible with existing simplex Versatile-Link connectors .
This product is lead free and compliant with RoHS.
Features
•
Compatible to IEEE 802.3 100BASE-FX PMA using POF
PMD
•
Link lengths up to 50m POF (NA0.5) or 70m POF (NA0.3)
•
Compact foot print
•
3.3V operation
•
LVPECL input and output data connections
•
LVPECL signal detect output
•
Temperature range -40°C to 85°C
Transmitter
The transmitter contains a 650nm LED with an integrated
driver. The LED driver operates at 3.3 V. It receives a LVPE-
CL/LVDS electrical input, and converts it into a modulated
current driving the LED. The LED is packaged in an optical
subassembly, part of the transmitter section. The optical
subassembly couples the output optical power efficiently
into POF fiber.
Applications
•
Industrial Ethernet and Fast Ethernet over polymer
optical fiber PMD
•
Networking in harsh environments like factory
automation or power generation and distribution
•
Supporting various Ethernet Fieldbus protocols
Receiver
The receiver utilizes a Si PIN photodiode. The PIN pho-
todiode is packaged in an optical sub-assembly, part of
the receiver section. This optical subassembly couples the
optical power efficiently from POF fiber to the receiving
PIN. The integrated IC operates at 3.3 V and converts the
photocurrent into LVPECL electrical output.
Di erential
Data Output
Signal
Detect Output
Integrated
Receiver
PIN Photodiode
Package
The transceiver package consists of three basic elements;
two opto-electical subassemblies and the housing as illus-
trated in the block diagrams in Figure 1. The package out-
line drawing and pin-outs are shown in Figures 2 and 5.
Di erential
Data Input
LED
Driver
LED
Figure 1. Block diagram.
Patent -
www.avagotech.com/patents
4.44
3.17
1.9
0.63
0
0.64
1.91
3.18
4.45
7.77
7.77
S T ANDOF F
AR E A (2 x 0.65 x 1.03)
8.89
6.35
3.05
0
∅
0. 9
+0 . 1
(8 x)
2
1
3
4
5
6
7
8
8.66
ND
LD G
S H I E
+0 . 1
( 2 x )
∅
1. 6
NOT E S :
1) Dimens ion: mm
2) G eneral tolerance: ±0.05
3.18
0
3) R ecommended P C B Thickness 1.57
±
0.05
4) P in des cription
MOUNT P OS T
UNP LAT E D (2x)
P IN
1
2
3
4
5
6
7
8
F UNC
T D+
T D-
T xV cc
G ND
R xVcc
SD
R D+
R D-
∅
3.2
+0.1
(2x)
3.73
S T ANDOF F
AR E A (4 x 1.9 x 1)
T op V iew
7.78
6.7
5.76
5.76
6.7
7.78
2.45
0
2.45
▼
F ront
▼
Figure 2. PCB footprint and Pin-out diagram.
The opto-electrical subassemblies utilize a high volume
assembly process together with low cost lens elements
which result in a cost effective building block. It consists
of the active III-V devices, IC chips and various surface
mounted passive components.
There are eight signal pins, four EMI shield solder posts
and two mounting posts, which exit the bottom of the
housing. The solder posts are isolated from the internal
circuit of the transceiver and are to be connected to chas-
sis ground. The mounting posts are to provide mechanical
strength to hold the transceiver to the application board.
Pin 4 GND: common ground pin. Directly connect this pin
to the signal ground plane of the host board.
Pin 5 RX Vcc: receiver power supply pin. Provide +3.3 V DC
via a receiver power supply filter circuit. Locate the power
supply filter circuit as close as possible to the Rx Vcc pin
Pin 6. SD: signal detect pin. If an optical signal is present
at the optical input, SD output is a logic “1”. Absence of an
optical input signal results in a logic “0” output. This pin
can be used to drive a LVPECL input of an upstream circuit,
such as Signal Detect input or Loss of Signal–bar.
Pin 7 RData+: receiver data out. This data line is a 3.3V
LVPECL compatible differential line which should be prop-
erly terminated.
Pin 8 RData-: receiver data out negative. This data line is a
3.3V LVPECL compatible differential line which should be
properly terminated. When SD is de-asserted, RData+ will
be set to logic “0” and RData- will be set to logic “1”.
Shield: This is to be connected to the equipment chassis
ground.
Pin Descriptions
Pin 1 TData+: transmitter data in. This input is a 3.3V LVPE-
CL/LVDS compatible differential line.
Pin 2 TData-: transmitter data in negative. This input is a
3.3V LVPECL/LVDS compatible differential line.
Pin 3 TX Vcc: transmitter power supply pin. Provide +3.3
V DC via a transmitter power supply filter circuit. Locate
the power supply filter circuit as close as possible to the
Tx Vcc pin.
2
Application circuit
The recommended application circuit is shown in figure 3.
1µH
VCC 3.3V
L1
1µH
10µF
100nF
C6
100nF
50
50
100nF
C1
TxVcc
TD+
100
R9
LED-Driver
K
A
100nF
C9
L2
Protocol IC & SERDES
TD+
TD-
C5
AFBR-5972Z
100nF
C2
TD-
C3
10µF
C7
150
R12
100nF
C8
RxVcc
RD+
RD-
R5
150
Amplifier and
K
quantizer
A
Tx
RD+
100
R1
RD-
50
50
100nF
Rx
LL
Chasis GND
C4
Signal detect
10k
R7
DGND
DGND
SD
GND
DGND
Figure 3. Recommended application circuit.
Board Layout – Decoupling Circuit and Ground Planes
It is important to take care of the layout of the application circuitry to achieve optimum performance of the transceiver.
A power supply decoupling circuit is recommended to filter out noise, to assure optimal product performance. It is
further recommended that a contiguous signal ground plane be provided in the circuit board directly under the trans-
ceiver to provide a low inductance ground for signal return current. It is also recommended that the shield posts be con-
nected to the chassis ground to provide optimum EMI, ESD and EMS performance. This recommendation is in keeping
with good high frequency board layout practices.
Regulatory compliance table
Feature
Electrostatic discharge (ESD)
to the electrical Pins
Immunity
Test Method
JESD22-A114
Variation of IEC 61000-4-3
Performance
Withstands up to 2000V HBM applied between the electrical pins.
Typically shows no measurable effect from a 15V/m field swept from
8MHz to 1GHz applied to the transceiver when mounted on a circuit
board without chassis enclosure.
Laser class 1 product (LED radiation only). TÜV certificate: R
72102396. Caution – Use of controls or adjustments of performance
or procedures other than those specified herein may result in haz-
ardous radiation exposure.
UL File #: E173874
Eye safety
EN 60825-1:52007
Component recognition
Underwriter Laboratories
3
LL
Table 2. Transceiver diagnostics timing characteristics
Parameter
Time to initialize
Hardware SD assert time
Hardware SD de-assert time
Symbol
t_init
t_sd_on
t_sd_off
Min
Max
5
100
100
Unit
ms
µs
µs
Notes
Note 1, figure 4
Note 2
Note 3
Notes:
1. Time from Power on to when the modulated optical output rises above 90% of nominal.
2. Time from valid optical signal to SD assertion.
3. Time from loss of optical signal to SD de-assertion.
TX, RX Vcc > 2.97V
OPTICAL SIGNAL
OCCURANCE
OF LOSS
SD
TRANSMITTER SIGNAL
t_init
t_sd_o
t_sd_on
t_init:
t_sd_on & t_sd_o
Figure 4. Transceiver timing diagrams
Absolute Maximum Ratings
Stresses in excess of the absolute maximum ratings can cause catastrophic damage to the device. Limits apply to each
parameter in isolation. all other parameters having values within the recommended operation conditions. It should not
be assumed that limiting values of more than one parameter can be applied to the products at the same time. Exposure
to the absolute maximum ratings for extended periods can adversely affect device reliability.
Parameter
Storage Temperature
Case Operating Temperature
Lead Soldering Temperature
Lead Soldering Time
Supply Voltage
Data Input Voltage
Differential Input Voltage
Output Current LVPECL
Symbol
T
S
T
C
T
sold
t
sold
V
CC
V
I
V
D
I
Dout
Min
-40
-40
Max
+100
+85
260
10
Unit
°C
°C
°C
s
V
V
V
mA
Notes
Note 4, 5
Note 6
Note 6
-0.5
-0.5
-45
4.0
Vcc
2.0
45
Peak to peak
Notes:
4. Operating the product outside the maximum rated case operating temperature range will compromise its reliability and may damage the product.
5. The temperature is measured using a thermocouple connected to the hottest position of the housing.
6. The transceiver is Pb-free wave solderable.
4
Recommended Operating Conditions
Parameter
Case Operating Temperature
Supply Voltage
Differential Input Voltage
Input common mode voltage
Data and Signal Detect Output Load
Signalling rate (Fast Ethernet)
Signalling rate (general)
Symbol
T
C
V
CC
V
D
V
IN_CM
R
L
B
FE
B
G
Min
-40
3.0
0.22
GND+0.8
Typ
3.3
0.8
50
125
Max
+85
3.6
1.6
VCC-0.8
Unit
°C
V
V
V
W
MBd
Notes
Note 1, 2
Peak to peak
4B/5B. Note 3
Note 4
10
125
MBd
Notes:
1. The temperature is measured using a thermocouple connected to the housing.
2. Electrical and optical specifications of the product are guaranteed across recommended case operating temperature range only.
3. Ethernet auto-negotiation pulses are not supported.
4. Evaluation of 10MBd was performed using a biphase code.
Transceiver Electrical Characteristics
Parameter
Supply Current
Power Dissipation
Power Supply Noise Reduction
Symbol
I
CC
P
DISS
P
SNR
Min
170
50
Typ
90
300
Max
120
436
Unit
mA
mW
mV
Notes
Note 5
Note 5
Peak to peak. Note 6
Notes
5. Characterized with LVPECL termination (82 Ohms to GND, 130 Ohms to V
CC
)
6. Fequencies from 0.1MHz to 100MHz.
Transmitter Optical Characteristics
Parameter
Average Launched Power
(1mm POF. NA=0.5)
Extinction ratio
Central Wavelength
Spectral bandwidth RMS
Optical Rise Time (10%-90%)
Optical Fall Time (90%-10%)
Duty Cycle Distortion Contributed
by the Transmitter
Data dependent jitter
Random Jitter Contributed
by the Transmitter
Overshoot
Symbol
Po
EXT
l
C
l
W
t
r
t
f
DCD
DDJ
RJ
Ov
Min
-10
10
635
Typ
-6.5
Max
-3.0
Unit
dBm
dB
Notes
Note 7
Note 7
Note 7
Notes 7, 8
Notes 7, 8
Note 7
Note 7
Peak to peak.
Notes 7, 9
Note 7
650
1.8
1.8
675
17
3.5
3.5
1.0
0.6
0.76
nm
nm
ns
ns
ns
ns
ns
%
7
25
Notes:
7. Measured at the end of 1 meter plastic optical fiber with a PRBS 2
7
-1 sequence.
8. 10%...90% or 90%...10% respectively
9. Based on BER=2.5x10
-10
5
