PD - 94528C
AFL5003R3S
50V Input, 3.3V Output
HYBRID-HIGH RELIABILITY
DC/DC CONVERTER
Description
The AFL Series of DC/DC converters feature high power
density with no derating over the full military temperature
range. This device is offered as part of a complete family
of converters providing single and dual output voltages
originally created to operate over a broad input voltage
range of 28V to 270V with output power ranging from
66W to 120W. For applications requiring higher output
power, multiple converters can be operated in parallel.
The internal current sharing circuits assure equal current
distribution among the paralleled converters. This series
incorporates International Rectifier’s proprietary
magnetic pulse feedback technology providing optimum
dynamic line and load regulation response. This
feedback system samples the output voltage at the pulse
width modulator fixed clock frequency, nominally 550
KHz. Multiple converters can be synchronized to a system
clock in the 500KHz to 700KHz range or to the
synchronization output of one converter. Under voltage
lockout, primary and secondary referenced inhibit, soft
start and load fault protection are provided on all models.
These converters are hermetically packaged in two
enclosure variations, utilizing copper core pins to
minimize resistive DC losses. Three lead styles are
available, each fabricated using International Rectifier’s
rugged ceramic lead-to-package seal assuring long term
hermeticity in the most harsh environments.
Manufactured in a facility fully qualified to MIL-PRF-
38534, these converters are fabricated utilizing DSCC
qualified processes. For available screening options,
refer to device screening table in the data sheet.
Variations in electrical, mechanical and screening can
be accommodated. Contact IR Santa Clara for special
requirements.
AFL
Features
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30V To 80V Input Range
3.3V Output
High Power Density - 50W/in3
66W Output Power
Parallel Operation with Stress and Current
Sharing
Low Profile (0.380") Seam Welded Package
Ceramic Feed thru Copper Core Pins
High Efficiency - to 74%
Full Military Temperature Range
Continuous Short Circuit and Overload
Protection
Remote Sensing Terminals
Primary and Secondary Referenced
Inhibit Functions
Line Rejection > 40dB - DC to 50KHz
External Synchronization Port
Fault Tolerant Design
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12/12/06
AFL5003R3S
Specifications
Absolute Maximum Ratings
Input voltage
Soldering temperature
Operating case temperature
Storage case temperature
-0.5V to +50VDC
300°C for 10 seconds
-55°C to +125°C
-65°C to +135°C
Electrical Performance Characteristics
-55°C < T
CASE
< +125°C, 30V< V
IN
< 80V
unless otherwise specified.
Parameter
INPUT VOLTAGE
OUTPUT VOLTAGE
1
2, 3
OUTPUT CURRENT
OUTPUT POWER
MAXIMUM CAPACITIVE LOAD
OUTPUT VOLTAGE
TEMPERATURE COEFFICIENT
OUTPUT VOLTAGE REGULATION
Line
Load
OUTPUT RIPPLE VOLTAGE
1, 2, 3
INPUT CURRENT
No Load
Inhibit 1
Inhibit 2
INPUT RIPPLE CURRENT
1, 2, 3
CURRENT LIMIT POINT
Expressed as a Percentage
of Full Rated Load
LOAD FAULT POWER DISSIPATION
Overload or Short Circuit
EFFICIENCY
SWITCHING FREQUENCY
ISOLATION
MTBF
1
2
3
VIN = 50 Volts,
1, 2, 3
1, 2, 3
1, 2, 3
1
Input to Output or Any Pin to Case
(except Pin 3). Test @ 500VDC
MIL-HDBK-217F, AIF @ TC = 40°C
VIN = 50 Volts, 100% Load
72
500
100
300
74
550
600
33
W
%
KHz
MΩ
KHrs
1
2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
4
VIN = 30, 50, 80 Volts,, Note 6
Note 6
Note 1
VIN = 50 Volts, 100% Load
Note 1, 6
No Load, 50% Load, 100% Load
VIN = 30, 50, 80 Volts,
VIN = 30, 50, 80 Volts,, 100% Load,
BW = 10MHz
VIN = 50 Volts,
I OUT = 0
Pin 4 Shorted to Pin 2
Pin 12 Shorted to Pin 8
VIN = 50 Volts, 100% Load
B.W. = 10MHz
V OUT = 90% V NOM
Note 5
115
105
125
125
115
140
%
10,000
-0.015
+0.015
Group A
Subgroups
Note 6
V IN = 50 Volts, 100% Load
Test Conditions
Min
30
3.27
3.23
Nom
50
3.30
Max
80
3.33
3.37
20
66
A
W
µF
%/°C
Unit
V
V
-20
-35
+20
+35
30
80
100
5.00
50
60
mV
mV pp
mA
mA pp
For Notes to Specifications, refer to page 3
2
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AFL5003R3S
Elecrical Performance Characteristics
(Continued)
Parameter
ENABLE INPUTS
(Inhibit Function)
Converter Off
Sink Current
Converter On
Sink Current
SYNCHRONIZATION INPUT
Frequency Range
Pulse Amplitude, Hi
Pulse Amplitude, Lo
Pulse Rise Time
Pulse Duty Cycle
LOAD TRANSIENT RESPONSE
Amplitude
Recovery
Amplitude
Recovery
LINE TRANSIENT RESPONSE
Amplitude
Recovery
TURN-ON CHARACTERISTICS
Overshoot
Delay
LOAD FAULT RECOVERY
LINE REJECTION
4, 5, 6
4, 5, 6
4, 5, 6
4, 5, 6
4, 5, 6
4, 5, 6
Group A
Subgroups
1, 2, 3
1, 2, 3
Test Conditions
Logical Low, Pin 4 or Pin 12
Note 1
Logical High, Pin 4 and Pin 12 - Note 9
Note 1
Min
-0.5
2.0
Nom
Max
0.8
100
50
100
700
10
0.8
100
80
Unit
V
µA
V
µA
KHz
V
V
ns
%
1, 2, 3
1, 2, 3
1, 2, 3
Note 1
Note 1
Note 2, 8
Load Step 50%
⇔
100%
Load Step 10%
⇔
50%
Note 1, 2, 3
VIN Step = 30
⇔
80 Volts
VIN = 30, 50, 80 Volts,. Note 4
Enable 1, 2 on. (Pins 4, 12 high or open)
Same as Turn On Characteristics.
MIL-STD-461, CS101, 30Hz to 50KHz
Note 1
500
2.0
-0.5
20
-450
-450
450
200
450
400
mV
µs
mV
µs
-500
500
500
mV
µs
250
120
mV
ms
40
50
dB
Notes to Specifications:
1.
2.
3.
4.
5.
6.
7.
8.
9.
Parameters not 100% tested but are guaranteed to the limits specified in the table.
Recovery time is measured from the initiation of the transient to where V
OUT
has returned to within
±1.0%
of
V
OUT
at 50% load.
Line transient transition time
≥
100µs.
Turn-on delay is measured with an input voltage rise time of between 100V and 500V per millisecond.
Current limit point is that condition of excess load causing output voltage to drop to 90% of nominal.
Parameter verified as part of another test.
All electrical tests are performed with the remote sense leads connected to the output leads at the load.
Load transient transition time
≥
10µs.
Enable inputs internally pulled high. Nominal open circuit voltage
≈
4.0VDC.
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AFL5003R3S
Block Diagram
Figure I. AFL Single Output
+ Input 1
Input
Filter
Primary
Bias Supply
Current
Sense
Sync Output
5
Control
FB
Enable 1 4
Output
Filter
7
10
+Output
+Sense
Sync Input 6
Case
3
Error
Amp
& Ref
Share
Amplifier
Sense
Amplifier
11 Share
12 Enable 2
9
8
Return Sense
Output Return
Input Return 2
Circuit Operation and Application Information
The AFL series of converters employ a forward switched
mode converter topology. (refer to Figure I.) Operation of
the device is initiated when a DC voltage whose magnitude
is within the specified input limits is applied between pins 1
and 2. If pin 4 is enabled (at a logical 1 or open) the primary
bias supply will begin generating a regulated housekeeping
voltage bringing the circuitry on the primary side of the
converter to life. Two power MOSFETs used to chop the
DC input voltage into a high frequency square wave, apply
this chopped voltage to the power transformer. As this
switching is initiated, a voltage is impressed on a second
winding of the power transformer which is then rectified and
applied to the primary bias supply. When this occurs, the
input voltage is shut out and the primary bias voltage
becomes exclusively internally generated.
The switched voltage impressed on the secondary output
transformer winding is rectified and filtered to provide the
converter output voltage. An error amplifier on the secondary
side compares the output voltage to a precision reference
and generates an error signal proportional to the difference.
This error signal is magnetically coupled through the
feedback transformer into the controller section of the
converter varying the pulse width of the square wave signal
driving the MOSFETs, narrowing the width if the output
voltage is too high and widening it if it is too low.
not used, the sense leads should be connected to their
respective output terminals at the converter. Figure III.
illustrates a typical application.
Inhibiting Converter Output (Enable)
As an alternative to application and removal of the DC
voltage to the input, the user can control the converter
output by providing TTL compatible, positive logic signals
to either of two enable pins (pin 4 or 12). The distinction
between these two signal ports is that enable 1 (pin 4) is
referenced to the input return (pin 2) while enable 2 (pin 12)
is referenced to the output return (pin 8). Thus, the user
has access to an inhibit function on either side of the isolation
barrier. Each port is internally pulled “high” so that when
not used, an open connection on both enable pins permits
normal converter operation. When their use is desired, a
logical “low” on either port will shut the converter down.
Figure II. Enable Input Equivalent Circuit
+5.6 V
100K
Pin 4 or
Pin 12
1N4148
290K
2N3904
180K
Pin 2 or
Pin 8
Disable
Remote Sensing
Connection of the
+
and
-
sense leads at a remotely located
load permits compensation for resistive voltage drop
between the converter output and the load when they are
physically separated by a significant distance. This
connection allows regulation to the placard voltage at the
point of application. When the remote sensing features is
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AFL5003R3S
Internally, these ports differ slightly in their function. In use,
a low on Enable 1 completely shuts down all circuits in the
converter while a low on Enable 2 shuts down the secondary
side while altering the controller duty cycle to near zero.
Enabling by the use of either port is transparent to the user
save for minor differences in idle current. (See specification
table).
high
l
evel of +2.0V. The sync output of another converter
which has been designated as the master oscillator provides
a convenient frequency source for this mode of operation.
When external synchronization is not required, the sync in
pin should be left unconnected there by permitting the
converter to operate at its’ own internally set frequency.
The sync output signal is a continuous pulse train set at
550
±
50KHz, with a duty cycle of 15
±
5.0%. This signal is
referenced to the input return and has been tailored to be
compatible with the AFL sync input port. Transition times
are less than 100ns and the low level output impedance is
less than 50Ω. This signal is active when the DC input
voltage is within the specified operating range and the
converter is not inhibited. This output has adequate drive
reserve to synchronize at least five additional converters.
A typical synchronization connection option is illustrated in
Figure III.
Synchronization of Multiple Converters
When operating multiple converters, system requirements
often dictate operation of the converters at a common
frequency. To accommodate this requirement, the AFL
series converters provide both a synchronization input and
output.
The sync input port permits synchronization of an AFL
converter to any compatible external frequency source
operating between 500KHz and 700KHz. This input signal
should be referenced to the input return and have a 10% to
90% duty cycle. Compatibility requires transition times less
than 100ns, maximum low level of +0.8V and a minimum
Figure III. Preferred Connection for Parallel Operation
Power
Input
1
12
Vin
Rtn
Case
Enable 1
Sync Out
Sync In
6
Enable 2
Share
AFL
+ Sense
- Sense
Return
+ Vout
7
Optional
Synchronization
Connection
Share Bus
1
12
Vin
Rtn
Case
Enable 1
Sync Out
Sync In
6
Enable 2
Share
AFL
+ Sense
- Sense
Return
+ Vout
7
to Load
1
12
Vin
Rtn
Case
Enable 1
Sync Out
Sync In
6
Enable 2
Share
AFL
+ Sense
- Sense
Return
+ Vout
7
(Other Converters)
Parallel Operation-Current and Stress Sharing
Figure III. illustrates the preferred connection scheme for
operation of a set of AFL converters with outputs operating
in parallel. Use of this connection permits equal sharing of a
load current exceeding the capacity of an individual AFL
among the members of the set. An important feature of the
AFL series operating in the parallel mode is that in addition
to sharing the current, the stress induced by temperature
will also be shared. Thus if one member of a paralleled set
is operating at a higher case temperature, the current it
provides to the load will be reduced as compensation for
the temperature induced stress on that device.
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