Revision 4
Fusion Family of Mixed Signal FPGAs
Features and Benefits
High-Performance Reprogrammable Flash Technology
•
•
•
•
Advanced 130-nm, 7-Layer Metal, Flash-Based CMOS Process
Nonvolatile, Retains Program when Powered Off
Instant On Single-Chip Solution
350 MHz System Performance
In-System Programming (ISP) and Security
• ISP with 128-Bit AES via JTAG
• FlashLock
®
Designed to Protect FPGA Contents
Advanced Digital I/O
• 1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation
• Bank-Selectable I/O Voltages – Up to 5 Banks per Chip
• Single-Ended I/O Standards: LVTTL, LVCMOS
3.3 V / 2.5 V /1.8 V / 1.5 V, 3.3 V PCI / 3.3 V PCI-X, and
LVCMOS 2.5 V / 5.0 V Input
• Differential I/O Standards: LVPECL, LVDS, B-LVDS, M-LVDS
– Built-In I/O Registers
– 700 Mbps DDR Operation
• Hot-Swappable I/Os
• Programmable Output Slew Rate, Drive Strength, and Weak
Pull-Up/Down Resistor
• Pin-Compatible Packages across the Fusion
®
Family
Embedded Flash Memory
• User Flash Memory – 2 Mbits to 8 Mbits
– Configurable 8-, 16-, or 32-Bit Datapath
– 10 ns Access in Read-Ahead Mode
• 1 Kbit of Additional FlashROM
Integrated A/D Converter (ADC) and Analog I/O
Up to 12-Bit Resolution and up to 600 Ksps
Internal 2.56 V or External Reference Voltage
ADC: Up to 30 Scalable Analog Input Channels
High-Voltage Input Tolerance: –10.5 V to +12 V
Current Monitor and Temperature Monitor Blocks
Up to 10 MOSFET Gate Driver Outputs
– P- and N-Channel Power MOSFET Support
– Programmable 1, 3, 10, 30 µA, and 20 mA Drive Strengths
• ADC Accuracy is Better than 1%
•
•
•
•
•
•
SRAMs and FIFOs
• Variable-Aspect-Ratio 4,608-Bit SRAM Blocks (×1, ×2, ×4, ×9,
and ×18 organizations available)
• True Dual-Port SRAM (except ×18)
• Programmable Embedded FIFO Control Logic
On-Chip Clocking Support
•
•
•
•
Internal 100 MHz RC Oscillator (accurate to 1%)
Crystal Oscillator Support (32 KHz to 20 MHz)
Programmable Real-Time Counter (RTC)
6 Clock Conditioning Circuits (CCCs) with 1 or 2 Integrated PLLs
– Phase Shift, Multiply/Divide, and Delay Capabilities
– Frequency: Input 1.5–350 MHz, Output 0.75–350 MHz
Soft ARM Cortex-M1 Fusion Devices (M1)
• ARM
®
Cortex-™M1–Enabled
Pigeon Point ATCA IP Support (P1)
• Targeted to Pigeon Point
®
Board Management Reference
(BMR) Starter Kits
• Designed in Partnership with Pigeon Point Systems
• ARM Cortex-M1 Enabled
• Targeted to Advanced Mezzanine Card (AdvancedMC™ Designs)
• Designed in Partnership with MicroBlade
• 8051-Based Module Management Controller (MMC)
Low Power Consumption
• Single 3.3 V Power Supply with On-Chip 1.5 V Regulator
• Sleep and Standby Low-Power Modes
MicroBlade Advanced Mezzanine Card Support (U1)
Table 1 • Fusion Family
Fusion Devices
ARM Cortex-M1
*
Devices
Pigeon Point Devices
MicroBlade Devices
System Gates
General
Information
Tiles (D-flip-flops)
Secure (AES) ISP
PLLs
Globals
Flash Memory Blocks (2 Mbits)
Total Flash Memory Bits
Memory
FlashROM Bits
RAM Blocks (4,608 bits)
RAM kbits
Analog Quads
Analog Input Channels
Analog and I/Os
Gate Driver Outputs
I/O Banks (+ JTAG)
Maximum Digital I/Os
Analog I/Os
90,000
2,304
Yes
1
18
1
2M
1,024
6
27
5
15
5
4
75
20
U1AFS250
250,000
6,144
Yes
1
18
1
2M
1,024
8
36
6
18
6
4
114
24
AFS090
AFS250
M1AFS250
AFS600
M1AFS600
P1AFS600
U1AFS600
600,000
13,824
Yes
2
18
2
4M
1,024
24
108
10
30
10
5
172
40
AFS1500
M1AFS1500
P1AFS1500
U1AFS1500
1,500,000
38,400
Yes
2
18
4
8M
1,024
60
270
10
30
10
5
252
40
Note:
*Refer to the
Cortex-M1
product brief for more information.
January 2013
© 2013 Microsemi Corporation
I
Fusion Family of Mixed Signal FPGAs
Fusion Device Architecture Overview
Bank 0
Bank 1
CCC
SRAM Block
4,608-Bit Dual-Port SRAM
or FIFO Block
OSC
I/Os
CCC/PLL
VersaTile
Bank 4
Bank 2
ISP AES
Decryption
User Nonvolatile
FlashROM
Charge Pumps
SRAM Block
4,608-Bit Dual-Port SRAM
or FIFO Block
Flash Memory Blocks
ADC
Flash Memory Blocks
Analog
Quad
Analog
Quad
Analog
Quad
Analog
Quad
Analog
Quad
Analog
Quad
Analog
Quad
Analog
Quad
Analog
Quad
Analog
Quad
CCC
Figure 1 •
Bank 3
Fusion Device Architecture Overview (AFS600)
Package I/Os: Single-/Double-Ended (Analog)
Fusion Devices
ARM Cortex-M1 Devices
Pigeon Point Devices
MicroBlade Devices
QN108
QN180
PQ208
3
FG256
FG484
FG676
75/22 (20)
37/9 (16)
60/16 (20)
65/15 (24)
93/26 (24)
114/37 (24)
95/46 (40)
119/58 (40)
172/86 (40)
119/58 (40)
223/109 (40)
252/126 (40)
U1AFS250
2
AFS090
AFS250
M1AFS250
AFS600
M1AFS600
P1AFS600
1
AFS1500
M1AFS1500
P1AFS1500
1
U1AFS1500
2
U1AFS600
2
Notes:
1. Pigeon Point devices are only offered in FG484 and FG256.
2. MicroBlade devices are only offered in FG256.
3. Fusion devices in the same package are pin compatible with the exception of the PQ208 package (AFS250 and AFS600).
II
R ev i si o n 4
Fusion Family of Mixed Signal FPGAs
Product Ordering Codes
M1AFS600
_
1
FG
G
256
Y
I
Application (junction temperature range)
Blank = Commercial (0 to +85°C)
I = Industrial (–40 to +100°C)
PP = Pre-Production
ES = Engineering Silicon (room temperature only)
Security Feature
Y = Device Includes License to Implement IP Based on
the Cryptography Research, Inc. (CRI) Patent Portfolio
Blank = Device Does Not Include License to Implement IP Based
on the Cryptography Research, Inc. (CRI) Patent Portfolio
Package Lead Count
Lead-Free Packaging Options
Blank = Standard Packaging
G = RoHS-Compliant (green) Packaging
Package Type
1
QN = Quad Flat No Lead (0.5 mm pitch)
PQ = Plastic Quad Flat Pack (0.5 mm pitch)
2
FG = Fine Pitch Ball Grid Array (1.0 mm pitch)
Speed Grade
Blank = Standard
1 = 15% Faster than Standard
2 = 25% Faster than Standard
Part Number
Fusion Devices
AFS090 =
AFS250 =
AFS600 =
AFS1500 =
90,000 System Gates
250,000 System Gates
600,000 System Gates
1,500,000 System Gates
ARM-Enabled Fusion Devices
M1AFS250 = 250,000 System Gates
M1AFS600 = 600,000 System Gates
M1AFS1500 = 1,500,000 System Gates
Pigeon Point Devices
P1AFS600 = 600,000 System Gates
P1AFS1500 = 1,500,000 System Gates
MicroBlade Devices
U1AFS250 = 250,000 System Gates
U1AFS600 = 600,000 System Gates
U1AFS1500 = 1,500,000 System Gates
Notes:
1. For Fusion devices, Quad Flat No Lead packages are only offered as RoHS compliant, QNG packages.
2. MicroBlade and Pigeon Point devices only support FG packages.
Fusion Device Status
Fusion
AFS090
AFS250
AFS600
AFS1500
Status
Production
Production
Production
Production
M1AFS250
M1AFS600
M1AFS1500
Production
Production
Production
P1AFS600
P1AFS1500
Production
Production
U1AFS250
U1AFS600
U1AFS1500
Production
Production
Production
Cortex-M1
Status
Pigeon Point
Status
MicroBlade
Status
R e visi on 4
III
Fusion Family of Mixed Signal FPGAs
Temperature Grade Offerings
Fusion Devices
ARM Cortex-M1 Devices
Pigeon Point Devices
MicroBlade Devices
QN108
QN180
PQ208
FG256
FG484
FG676
C, I
C, I
–
C, I
–
–
U1AFS250
4
–
C, I
C, I
C, I
–
–
AFS090
AFS250
M1AFS250
AFS600
M1AFS600
P1AFS600
3
U1AFS600
4
–
–
C, I
C, I
C, I
–
AFS1500
M1AFS1500
P1AFS1500
3
U1AFS1500
4
–
–
–
C, I
C, I
C, I
Notes:
1. C = Commercial Temperature Range: 0°C to 85°C Junction
2. I = Industrial Temperature Range: –40°C to 100°C Junction
3. Pigeon Point devices are only offered in FG484 and FG256.
4. MicroBlade devices are only offered in FG256.
Speed Grade and Temperature Grade Matrix
Std.
1
C
3
I
4
–1
–2
2
3
3
3
3
3
3
Notes:
1. MicroBlade devices are only offered in standard speed grade.
2. Pigeon Point devices are only offered in –2 speed grade.
3. C = Commercial Temperature Range: 0°C to 85°C Junction
4. I = Industrial Temperature Range: –40°C to 100°C Junction
Contact your local Microsemi SoC Products Group representative for device availability:
http://www.microsemi.com/soc/contact/offices/index.html.
Cortex-M1, Pigeon Point, and MicroBlade Fusion Device Information
This datasheet provides information for all Fusion (AFS), Cortex-M1 (M1), Pigeon Point (P1), and MicroBlade (U1) devices. The
remainder of the document will only list the Fusion (AFS) devices. Please apply relevant information to M1, P1, and U1 devices
when appropriate. Please note the following:
•
•
•
Cortex-M1 devices are offered in the same speed grades and packages as basic Fusion devices.
Pigeon Point devices are only offered in –2 speed grade and FG484 and FG256 packages.
MicroBlade devices are only offered in standard speed grade and the FG256 package.
IV
R ev i si o n 4
Fusion Family of Mixed Signal FPGAs
Table of Contents
Fusion Device Family Overview
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
Unprecedented Integration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4
Related Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-10
Device Architecture
Fusion Stack Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
Core Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
Clocking Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-19
Real-Time Counter System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-33
Embedded Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-41
Analog Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-79
Analog Configuration MUX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-129
User I/Os . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-135
Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-226
Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-231
DC and Power Characteristics
General Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
Calculating Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10
Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-32
Package Pin Assignments
QN108
QN180
PQ208
FG256
FG484
FG676
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-11
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-19
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-27
Datasheet Information
List of Changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1
Datasheet Categories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-17
Safety Critical, Life Support, and High-Reliability Applications Policy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-17
Revision 4
V
DSP 与 ARM 处理器
