Advanced v0.1
IGLOO
TM
Low-Power Flash FPGAs with Flash*Freeze
TM
Technology
Features and Benefits
Low Power
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1.2 V or 1.5 V Core Voltage for Low Power
Supports Single-Voltage System Operation
5 µW Power Consumption in Flash*Freeze Mode
Low-Power Active FPGA Operation (from 25 µW)
Flash*Freeze Technology Enables Ultra-Low Power
Consumption while Maintaining FPGA Content
Flash*Freeze Pin Allows Easy Entry To / Exit From Ultra-
Low-Power Flash*Freeze Mode
30 k to 1 Million System Gates
Up to 144 kbits of True Dual-Port SRAM
Up to 300 User I/Os
130-nm, 7-Layer Metal (6 Copper), Flash-Based CMOS
Process
Live-at-Power-Up (LAPU) Level 0 Support
Single-Chip Solution
Retains Programmed Design When Powered Off
Secure ISP Using On-Chip 128-Bit Advanced Encryption
Standard (AES) Decryption (except AGL030 devices) via
JTAG (IEEE 1532–compliant)
FlashLock
®
to Secure FPGA Contents
Segmented, Hierarchical Routing and Clock Structure
High-Performance, Low-Skew Global Network
Architecture Supports Ultra-High Utilization
®
Advanced I/O
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700 Mbps DDR, LVDS-Capable I/Os (AGL250 and above)
1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation
Bank-Selectable I/O Voltages—Up to 4 Banks per Chip
Single-Ended I/O Standards: LVTTL, LVCMOS 3.3 V /
2.5 V / 1.8 V / 1.5 V, 3.3 V PCI / 3.3 V PCI-X (except
AGL030), and LVCMOS 2.5 V / 5.0 V Input
Differential I/O Standards: LVPECL, LVDS, BLVDS, and
M-LVDS (AGL250 and above)
I/O Registers on Input, Output, and Enable Paths
Hot-Swappable and Cold Sparing I/Os (AGL030 only)
Programmable Output Slew Rate (except AGL030) and
Drive Strength
Weak Pull-Up/Down
IEEE 1149.1 (JTAG) Boundary Scan Test
Pin-Compatible Packages Across the IGLOO Family
Six CCC Blocks, One with an Integrated PLL
Configurable Phase-Shift, Multiply/Divide, Delay
Capabilities and External Feedback, Multiply/Divide,
Delay Capabilities, and External Feedback
Wide Input Frequency Range (1.5 MHz up to 250 MHz)
1 kbit of FlashROM User-Nonvolatile Memory
SRAMs and FIFOs with Variable-Aspect-Ratio 4,608-Bit
RAM Blocks (×1, ×2, ×4, ×9, and ×18 organizations
available)
True Dual-Port SRAM (except ×18)
High Capacity
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Reprogrammable Flash Technology
Clock Conditioning Circuit (CCC) and PLL
(except
AGL030)
In-System Programming (ISP) and Security
Embedded Memory
High-Performance Routing Hierarchy
Table 1 •
IGLOO Product Family
AGL030
30 k
768
in
IGLOO Devices
System Gates
VersaTiles (D-flip-flops)
Quiescent Current (typical)
Flash*Freeze Mode (µA)
RAM kbits (1,024 bits)
4,608-Bit Blocks
FlashROM Bits
Secure (AES) ISP
Integrated PLL in CCCs
VersaNet Globals
1
I/O Banks
Maximum User I/Os
Package Pins
CS
QFN
VQFP
FBGA
AGL060
60 k
1,536
3
AGL125
125 k
3,072
AGL250
250 k
6,144
AGL600
600 k
13,824
AGL1000
1M
24,576
4
–
–
1k
–
–
6
2
81
8
18
4
1k
Yes
1
18
2
96
CS196
QN132
VQ100
FG144
14
36
8
1k
Yes
1
18
2
133
CS196
QN132
VQ100
FG144
28
36
8
1k
Yes
1
18
4
143
CS196
3
QN132
VQ100
FG144
60
108
24
1k
Yes
1
18
4
235
102
144
32
1k
Yes
1
18
4
300
QN132
VQ100
FG144, FG256,
FG484
FG144, FG256,
FG484
Notes:
1. Six chip (main) and twelve quadrant global networks are available for AGL060 and above.
2. For higher densities and support of additional features, refer to the
IGLOO™e Low-Power Flash FPGAs with Flash*Freeze Technology
datasheet.
3. Device/package support TBD.
June 2007
© 2007 Actel Corporation
i
See the Actel website for the latest version of the datasheet.
IGLOO Low-Power Flash FPGAs with Flash*Freeze Technology
I/Os Per Package
1
IGLOO Devices
AGL030
AGL060
6
AGL125
AGL250
2
AGL600
Differential I/O Pairs
AGL1000
Differential I/O Pairs
–
–
–
25
44
74
I/O Type
Differential I/O Pairs
2
2
2
Single-Ended I/O
Single-Ended I/O
Single-Ended I/O
Single-Ended I/O
Single-Ended I/O
Package
Dimensions (mm)
VQ100 (14 × 14)
QN132 (8 × 8)
CS196 (8 × 8)
FG144 (13 × 13)
FG256 (17 × 17)
FG484 (23 × 23)
Notes:
79
81
–
–
–
–
71
80
96
96
–
–
71
84
133
97
–
–
68
87
143
6
97
–
–
13
19
30
6
24
–
–
97
177
235
–
–
–
25
43
60
97
177
300
1. When considering migrating your design to a lower- or higher-density device, refer to
"Package Pin Assignments"
starting on
page
4-1
to ensure compliance with design and board migration requirements.
2. Each used differential I/O pair reduces the number of single-ended I/Os available by two.
3. FG256 and FG484 are footprint-compatible packages.
4. When the Flash*Freeze pin is used to directly enable Flash*Freeze mode and not used as a regular I/O, the number of single-ended
user I/Os available is reduced by one.
5. "G" indicates RoHS-compliant packages. Refer to
"IGLOO Ordering Information" on page iii
for the location of the "G" in the part
number.
6. Device/package support TBD.
Packaging Tables
Pinout tables not published in this document will be added in future revisions of the datasheet. For updates, contact
your local Actel sales representative.
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A d v a n c e d v 0 .1
Single-Ended I/O
–
–
–
IGLOO Low-Power Flash FPGAs with Flash*Freeze Technology
IGLOO Ordering Information
AGL1000
V2
_
FG
G
144
I
Application (Temperature Range)
Blank =
Commercial
(0°C to +70°C)
I = Industrial (
–
40°C to +85°C)
PP = Pre-Production
ES = Engineering
Sample
(Room Temperature Only)
Package Lead
Count
Lead-Free Packaging
Blank =
Standard
Packaging
G=
RoHS-Compliant Packaging
Package Type
CS
=
Chip Scale
Package (0.5 mm pitch)
QN = Quad Flat Pack No Leads (0.5 mm pitch)
VQ = Very Thin Quad Flat Pack (0.5 mm pitch)
FG = Fine Pitch Ball
Grid
Array (1.0 mm pitch)
Speed Grade
F = 20%
Slower
than
Standard*
Blank =
Standard
Supply
Voltage
2 = 1.2 V or 1.5 V
5 = 1.5 V
Part Number
IGLOO Devices
AGL030 =
AGL060 =
AGL125 =
AGL250 =
AGL600 =
AGL1000 =
30,000
System Gates
60,000 System Gates
125,000
System Gates
250,000
System Gates
600,000 System Gates
1,000,000
System Gates
Note:
*The DC and switching characteristics for the –F speed grade targets are based only on simulation.
The characteristics provided for the –F speed grade are subject to change after establishing FPGA specifications. Some restrictions
might be added and will be reflected in future revisions of this document. The –F speed grade is only supported in the commercial
temperature range.
A d v an c ed v0 . 1
iii
IGLOO Low-Power Flash FPGAs with Flash*Freeze Technology
Temperature Grade Offerings
Package
QN132
VQ100
CS196
FG144
FG256
FG484
Notes:
1. C = Commercial temperature range: 0°C to 70°C
2. I = Industrial temperature range: –40°C to 85°C
3. Device/package support TBD
AGL030
C, I
C, I
–
–
–
–
AGL060
C, I
C, I
C, I
C, I
–
–
3
AGL125
C, I
C, I
C, I
C, I
–
–
AGL250
C, I
C, I
C, I
–
–
3
AGL600
–
–
–
C, I
C, I
C, I
AGL1000
–
–
–
C, I
C, I
C, I
C, I
Speed Grade and Temperature Grade Matrix
Temperature Grade
C
2
I
3
–F
✓
–
1
Std.
✓
✓
Notes:
1. The characteristics provided for the –F speed grade are subject to change after establishing FPGA specifications. Some restrictions
might be added and will be reflected in future revisions of this document. The –F speed grade is only supported in the commercial
temperature range.
2. C = Commercial temperature range: 0°C to 70°C
3. I = Industrial temperature range: –40°C to 85°C
Contact your local Actel representative for device availability (http://www.actel.com/contact/default.aspx).
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A d v a n c e d v 0 .1
IGLOO Low-Power Flash FPGAs with Flash*Freeze Technology
Table of Contents
Introduction and Overview
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
Related Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7
Device Architecture
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
Device Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
Flash*Freeze Technology and Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . 2-50
Power Conservation Techniques . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-50
Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-58
Software Tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-61
Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-61
Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-61
ISP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-62
DC and Switching Characteristics
General Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
Calculating Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6
User I/O Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-15
VersaTile Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-77
Global Resource Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-83
Embedded SRAM and FIFO Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-87
Embedded FlashROM Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-102
JTAG 1532 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-103
Package Pin Assignments
132-Pin QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1
100-Pin VQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6
144-Pin FBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-9
256-Pin FBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-14
Datasheet Information
Datasheet Categories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1
Export Administration Regulations (EAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1
Advanced v0.1
v
