Revision 19
IGLOO Low Power Flash FPGAs
with Flash*Freeze Technology
Features and Benefits
Low Power
•
•
•
•
•
1.2 V to 1.5 V Core Voltage Support for Low Power
Supports Single-Voltage System Operation
5 µW Power Consumption in Flash*Freeze Mode
Low Power Active FPGA Operation
Flash*Freeze Technology Enables Ultra-Low Power
Consumption while Maintaining FPGA Content
• Easy Entry to / Exit from Ultra-Low Power Flash*Freeze Mode
• 1.2 V, 1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation
• Bank-Selectable I/O Voltages—up to 4 Banks per Chip
• Single-Ended I/O Standards: LVTTL, LVCMOS
3.3 V / 2.5 V / 1.8 V / 1.5 V / 1.2 V, 3.3 V PCI / 3.3 V PCI-X
†
,
and LVCMOS 2.5 V / 5.0 V Input
†
• Differential I/O Standards: LVPECL, LVDS, B-LVDS, and M-
LVDS (AGL250 and above)
• Wide Range Power Supply Voltage Support per JESD8-B,
Allowing I/Os to Operate from 2.7 V to 3.6 V
• Wide Range Power Supply Voltage Support per JESD8-12,
Allowing I/Os to Operate from 1.14 V to 1.575 V
• I/O Registers on Input, Output, and Enable Paths
• Hot-Swappable and Cold-Sparing I/Os
‡
• Programmable Output Slew Rate
†
and Drive Strength
• Weak Pull-Up/-Down
• IEEE 1149.1 (JTAG) Boundary Scan Test
• Pin-Compatible Packages across the IGLOO Family
†
• Six CCC Blocks, One with an Integrated PLL
• Configurable Phase Shift, Multiply/Divide, Delay Capabilities,
and External Feedback
• Wide Input Frequency Range (1.5 MHz up to 250 MHz)
High Capacity
• 15K to 1 Million System Gates
• Up to 144 Kbits of True Dual-Port SRAM
• Up to 300 User I/Os
Reprogrammable Flash Technology
•
•
•
•
•
130-nm, 7-Layer Metal, Flash-Based CMOS Process
Live-at-Power-Up (LAPU) Level 0 Support
Single-Chip Solution
Retains Programmed Design When Powered Off
250 MHz (1.5 V systems) and 160 MHz (1.2 V systems) System
Performance
Clock Conditioning Circuit (CCC) and PLL
In-System Programming (ISP) and Security
• ISP Using On-Chip 128-Bit Advanced Encryption Standard
(AES) Decryption (except ARM
®
-enabled IGLOO
®
devices) via
JTAG (IEEE 1532–compliant)
†
• FlashLock
®
Designed to Secure FPGA Contents
Embedded Memory
• 1 kbit of FlashROM User Nonvolatile Memory
• SRAMs and FIFOs with Variable-Aspect-Ratio 4,608-Bit
†
RAM
Blocks (×1, ×2, ×4, ×9, and ×18 organizations)
• True Dual-Port SRAM (except ×18)
†
High-Performance Routing Hierarchy
• Segmented, Hierarchical Routing and Clock Structure
ARM Processor Support in IGLOO FPGAs
• M1 IGLOO Devices—Cortex™-M1 Soft Processor Available
with or without Debug
Advanced I/O
• 700 Mbps DDR, LVDS-Capable I/Os (AGL250 and above)
IGLOO Devices
AGL015
AGL030
AGL060 AGL125
AGL250
AGL400
AGL600
AGL1000
1
ARM-Enabled IGLOO Devices
M1AGL250
M1AGL600 M1AGL1000
System Gates
15,000
30,000
60,000 125,000
250,000
400,000
600,000
1,000,000
Typical Equivalent Macrocells
128
256
512
1,024
2,048
–
–
–
VersaTiles (D-flip-flops)
384
768
1,536
3,072
6,144
9,216
13,824
24,576
Flash*Freeze Mode (typical, µW)
5
5
10
16
24
32
36
53
RAM kbits (1,024 bits)
–
–
18
36
36
54
108
144
4,608-Bit Blocks
–
–
4
8
8
12
24
32
FlashROM Kbits (1,024 bits)
1
1
1
1
1
1
1
1
1
AES-Protected ISP
–
–
Yes
Yes
Yes
Yes
Yes
Yes
2
Integrated PLL in CCCs
–
–
1
1
1
1
1
1
3
VersaNet Globals
6
6
18
18
18
18
18
18
I/O Banks
2
2
2
2
4
4
4
4
Maximum User I/Os
49
81
96
133
143
194
235
300
Package Pins
UC/CS
UC81
CS121
2
CS121, CS81, CS196
4
CS196
CS281
CS281
CS81
CS196
QFN
QN68 QN48, QN68, QN132
QN132
4
QN132
QN132
VQFP
VQ100
VQ100
VQ100
VQ100
FBGA
FG144
FG144, FG256, FG144, FG256, FG144, FG256,
FG144
FG144
FG484
FG484
FG484
Notes:
1.
2.
3.
4.
5.
AES is not available for ARM-enabled IGLOO devices.
AGL060 in CS121 does not support the PLL.
Six chip (main) and twelve quadrant global networks are available for AGL060 and above.
The M1AGL250 device does not support this package.
The
IGLOOe
datasheet and
IGLOOe FPGA Fabric User’s Guide
provide information on higher densities and additional features.
† AGL015 and AGL030 devices do not support this feature.
September 2011
© 2011 Microsemi Corporation
‡ Supported only by AGL015 and AGL030 devices.
I
IGLOO Low Power Flash FPGAs
I/Os Per Package
1
IGLOO Devices
ARM-Enabled
IGLOO Devices
AGL015 AGL030 AGL060
AGL125
AGL250
M1AGL250
I/O
Single-Ended I/O
3
Single-Ended I/O
Single-Ended I/O
Single-Ended I/O
Single-Ended I/O
Type
2
Differential I/O Pairs
Differential I/O Pairs
Differential I/O Pairs
Differential I/O Pairs
–
–
–
–
–
–
–
–
25
44
53
74
FG484
529
1.0
2.23
Single-Ended I/O
3
Single-Ended I/O
3
Single-Ended I/O
3
–
–
–
–
–
–
–
–
97
177
215
300
FG256
289
1.0
1.60
AGL400
AGL600
M1AGL600
AGL1000
M1AGL1000
Package
QN48
QN68
UC81
CS81
CS121
VQ100
QN132
CS196
FG144
FG256
5
CS281
FG484
5
–
49
–
–
–
–
–
–
–
–
–
–
34
49
66
66
–
77
81
–
–
–
–
–
–
–
–
–
96
71
80
–
96
–
–
–
–
–
–
–
96
71
84
133
97
–
–
–
–
–
–
60
–
68
87
4
143
4
97
–
–
–
–
–
–
7
–
13
19
4
35
4
24
–
–
–
–
–
–
–
–
–
–
143
97
178
–
194
–
–
–
–
–
–
–
35
25
38
–
38
–
–
–
–
–
–
–
–
97
177
215
235
–
–
–
–
–
–
–
–
25
43
53
60
Notes:
1. When considering migrating your design to a lower- or higher-density device, refer to the
IGLOO FPGA Fabric User’s Guide
to
ensure compliance with design and board migration requirements.
2. When the Flash*Freeze pin is used to directly enable Flash*Freeze mode and not used as a regular I/O, the number of single-
ended user I/Os available is reduced by one.
3. Each used differential I/O pair reduces the number of single-ended I/Os available by two.
4. The M1AGL250 device does not support QN132 or CS196 packages.
5. FG256 and FG484 are footprint-compatible packages.
Table 1 • IGLOO FPGAs Package Sizes Dimensions
Package
Length × Width
(mm\mm)
Nominal Area
(mm
2
)
Pitch (mm)
Height (mm)
UC81
4×4
16
0.4
0.80
CS81
5
×
5
25
0.5
0.80
CS121
6×6
36
0.5
0.99
QN48
6×6
36
0.4
0.90
QN68
8×8
64
0.4
0.90
QN132
8×8
64
0.5
0.75
CS196
8×8
64
0.5
1.20
CS281
FG144
VQ100
10 × 10 13 × 13 14 × 14
100
0.5
1.05
169
1.0
1.45
196
0.5
1.00
17 × 17 23 × 23
II
R evis i o n 19
IGLOO Low Power Flash FPGAs
IGLOO Ordering Information
AGL1000
V2
_
FG
G
144
Y
I
Application (Temperature Range)
Blank = Commercial (0°C to +70°C Ambient Temperature)
I = Industrial (
–
40°C to +85°C Ambient Temperature)
PP = Pre-Production
ES = Engineering Sample (Room Temperature Only)
Security Feature
Y = Device Includes License to Implement IP Based on the
Cryptography Research, Inc. (CRI) Patent Portfolio
Package Lead Count
Lead-Free Packaging
Blank = Standard Packaging
G= RoHS-Compliant Packaging (some packages also halogen-free)
Package Type
UC = Micro Chip Scale Package (0.4 mm pitch)
CS = Chip Scale Package (0.4 mm and 0.5 mm pitches)
QN = Quad Flat Pack No Leads (0.4 mm and 0.5 mm pitch)
VQ = Very Thin Quad Flat Pack (0.5 mm pitch)
FG = Fine Pitch Ball Grid Array (1.0 mm pitch)
Supply Voltage
2 = 1.2 V to 1.5 V
5 = 1.5 V only
Part Number
IGLOO Devices
AGL015 = 15,000 System Gates
AGL030 = 30,000 System Gates
AGL060 = 60,000 System Gates
AGL125 = 125,000 System Gates
AGL250 = 250,000 System Gates
AGL400 = 400,000 System Gates
AGL600 = 600,000 System Gates
AGL1000 = 1,000,000 System Gates
IGLOO Devices with Cortex-M1
M1AGL250 = 250,000 System Gates
M1AGL600 = 600,000 System Gates
M1AGL1000 = 1,000,000 System Gates
Note:
Marking Information: IGLOO V2 devices do not have V2 marking, but IGLOO V5 devices are marked accordingly.
R ev i si o n 1 9
III
IGLOO Low Power Flash FPGAs
Temperature Grade Offerings
AGL015
Package
QN48
QN68
UC81
CS81
CS121
VQ100
QN132
CS196
FG144
FG256
CS281
FG484
–
C, I
–
–
–
–
–
–
–
–
–
–
C, I
–
C, I
C, I
–
C, I
C, I
–
–
–
–
–
–
–
–
–
C, I
C, I
C, I
–
C, I
–
–
–
–
–
–
–
C, I
C, I
C, I
C, I
C, I
–
–
–
AGL030
AGL060
AGL125
AGL250
M1AGL250
–
–
–
C, I
–
C, I
C, I
C, I
C, I
–
–
–
–
–
–
–
–
–
–
C, I
C, I
C, I
–
C, I
AGL400
AGL600
AGL1000
M1AGL600 M1AGL1000
–
–
–
–
–
–
–
–
C, I
C, I
C, I
C, I
–
–
–
–
–
–
–
–
C, I
C, I
C, I
C, I
C = Commercial temperature range: 0°C to 70°C ambient temperature.
I = Industrial temperature range: –40°C to 85°C ambient temperature.
IGLOO Device Status
IGLOO Devices
AGL015
AGL030
AGL060
AGL125
AGL250
AGL400
AGL600
AGL1000
Status
Production
Production
Production
Production
Production
Production
Production
Production
M1AGL600
M1AGL1000
Production
Production
M1AGL250
Production
M1 IGLOO Devices
Status
References made to IGLOO devices also apply to ARM-enabled IGLOOe devices. The ARM-enabled part numbers start with M1
(Cortex-M1).
Contact your local Microsemi SoC Products Group (formerly Actel) representative for device availability:
http://www.microsemi.com/soc/contact/default.aspx.
AGL015 and AGL030
The AGL015 and AGL030 are architecturally compatible; there are no RAM or PLL features.
IV
R evis i o n 19
IGLOO Low Power Flash FPGAs
Table of Contents
IGLOO Device Family Overview
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
IGLOO DC and Switching Characteristics
General Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
Calculating Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7
Power Calculation Methodology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-17
User I/O Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-20
VersaTile Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-100
Global Resource Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-106
Clock Conditioning Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-115
Embedded SRAM and FIFO Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-117
Embedded FlashROM Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-130
JTAG 1532 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-131
Pin Descriptions
Supply Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
User Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
JTAG Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Special Function Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Related Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-1
3-2
3-4
3-5
3-5
3-5
Package Pin Assignments
UC81 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1
CS81 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3
CS121 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6
CS196 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-11
CS281 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-18
QN48 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-25
QN68 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-27
QN132 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-30
VQ100 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-39
FG144 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-44
FG256 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-57
FG484 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-67
Datasheet Information
List of Changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1
Datasheet Categories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10
Safety Critical, Life Support, and High-Reliability Applications Policy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10
R ev i si o n 1 9
V
