Revision 19
DS0110
IGLOO nano Low Power Flash FPGAs
with Flash*Freeze Technology
Features and Benefits
Low Power
•
•
•
•
•
nanoPower Consumption—Industry’s Lowest Power
1.2 V to 1.5 V Core Voltage Support for Low Power
Supports Single-Voltage System Operation
Low Power Active FPGA Operation
Flash*Freeze Technology Enables Ultra-Low Power
Consumption while Maintaining FPGA Content
• Easy Entry to / Exit from Ultra-Low Power Flash*Freeze Mode
• As Small as 3x3 mm in Size
High-Performance Routing Hierarchy
Advanced I/Os
• Segmented, Hierarchical Routing and Clock Structure
• 1.2 V, 1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation
• Bank-Selectable I/O Voltages—up to 4 Banks per Chip
• Single-Ended I/O Standards: LVTTL, LVCMOS
3.3 V / 2.5 V / 1.8 V / 1.5 V / 1.2 V
• Wide Range Power Supply Voltage Support per JESD8-B,
Allowing I/Os to Operate from 2.7 V to 3.6 V
• Wide Range Power Supply Voltage Support per JESD8-12,
Allowing I/Os to Operate from 1.14 V to 1.575 V
• I/O Registers on Input, Output, and Enable Paths
• Selectable Schmitt Trigger Inputs
• Hot-Swappable and Cold-Sparing I/Os
• Programmable Output Slew Rate and Drive Strength
• Weak Pull-Up/-Down
• IEEE 1149.1 (JTAG) Boundary Scan Test
• Pin-Compatible Packages across the IGLOO
®
Family
†
• Up to Six CCC Blocks, One with an Integrated PLL
• Configurable Phase Shift, Multiply/Divide, Delay
Capabilities, and External Feedback
• Wide Input Frequency Range (1.5 MHz up to 250 MHz)
• 1 kbit of FlashROM User Nonvolatile Memory
• SRAMs and FIFOs with Variable-Aspect-Ratio 4,608-Bit RAM
Blocks (×1, ×2, ×4, ×9, and ×18 organizations)
†
• True Dual-Port SRAM (except × 18 organization)
†
• Tj = -20°C to +85°C
Small Footprint Packages
Wide Range of Features
Reprogrammable Flash Technology
•
•
•
•
•
130-nm, 7-Layer Metal, Flash-Based CMOS Process
Instant On Level 0 Support
Single-Chip Solution
Retains Programmed Design When Powered Off
250 MHz (1.5 V systems) and 160 MHz (1.2 V systems) System
Performance
• 10,000 to 250,000 System Gates
• Up to 36 kbits of True Dual-Port SRAM
• Up to 71 User I/Os
Clock Conditioning Circuit (CCC) and PLL
In-System Programming (ISP) and Security
Embedded Memory
• ISP Using On-Chip 128-Bit Advanced Encryption Standard
(AES) Decryption via JTAG (IEEE 1532–compliant)
• FlashLock
®
Designed to Secure FPGA Contents
• 1.2 V Programming
Enhanced Commercial Temperature Range
AGLN060
AGLN030Z
1
IGLOO nano Devices
IGLOO nano-Z Devices
System Gates
Typical Equivalent Macrocells
VersaTiles (D-flip-flops)
Flash*Freeze Mode (typical, µW)
RAM Kbits (1,024 bits)
2
4,608-Bit Blocks
Secure (AES)
2
1
AGLN010 AGLN015
1
AGLN020
10,000
86
260
2
–
–
1
–
2,3
AGLN125
1
AGLN250
1
AGLN060Z
60,000
512
1,536
10
18
4
1
Yes
1
18
2
71
71
AGLN125Z
125,000
1,024
3,072
16
36
8
1
Yes
1
18
2
71
71
AGLN250Z
1
250,000
2,048
6,144
24
36
8
1
Yes
1
18
4
68
68
15,000
128
384
4
–
–
1
–
–
4
3
49
–
20,000
172
520
4
–
–
1
–
–
4
3
52
52
30,000
256
768
5
–
–
1
–
–
6
2
77
83
FlashROM Kbits (1,024 bits)
ISP
2
Integrated PLL in CCCs
VersaNet Globals
I/O Banks
Maximum User I/Os (packaged device)
Maximum User I/Os (Known Good Die)
–
4
2
34
34
† AGLN030 and smaller devices do not support this feature.
October 2015
© 2015 Microsemi Corporation
I
IGLOO nano Devices
IGLOO nano-Z
Package Pins
UC/CS
QFN
VQFP
Devices
1
AGLN010 AGLN015
1
AGLN020
AGLN030Z
UC36
QN48
UC81,
CS81
QN68
1
AGLN060
AGLN060Z
CS81
VQ100
1
AGLN125
AGLN125Z
CS81
VQ100
1
AGLN250
AGLN250Z
1
CS81
VQ100
QN68
UC81, CS81
QN48, QN68
VQ100
Notes:
1. Not recommended for new designs. Few devices/packages are obsoleted. For more information on obsoleted devices/packages, refer
to the
PDN 1503 - IGLOO nano Z and ProASIC3 nano Z Families.
2. AGLN030 and smaller devices do not support this feature.
3. AGLN060, AGLN125, and AGLN250 in the CS81 package do not support PLLs.
4. For higher densities and support of additional features, refer to the
DS0095: IGLOO Low Power Flash FPGAs Datasheet
and
IGLOOe
Low-Power Flash FPGAs Datasheet
.
I/Os Per Package
IGLOO nano Devices
IGLOO nano-Z Devices
1
Known Good Die
UC36
QN48
QN68
UC81
CS81
VQ100
34
23
34
–
–
–
–
–
–
–
49
–
–
–
52
–
–
49
52
52
–
AGLN010
AGLN015
1
AGLN020
AGLN030Z
1
83
–
34
49
66
66
77
AGLN060
71
–
–
–
–
60
71
AGLN125
71
–
–
–
–
60
71
AGLN250
68
–
–
–
–
60
68
AGLN060Z
1
AGLN125Z
1
AGLN250Z
1
Notes:
1. Not recommended for new designs.
2. When considering migrating your design to a lower- or higher-density device, refer to the
DS0095: IGLOO Low Power Flash
FPGAs Datasheet
and
IGLOO FPGA Fabric User’s Guide
to ensure compliance with design and board migration requirements.
3. When the Flash*Freeze pin is used to directly enable Flash*Freeze mode and not used as a regular I/O, the number of single-
ended user I/Os available is reduced by one.
4. "G" indicates RoHS-compliant packages. Refer to
"IGLOO nano Ordering Information" on page IV
for the location of the "G" in
the part number. For nano devices, the VQ100 package is offered in both leaded and RoHS-compliant versions. All other
packages are RoHS-compliant only.
Table 1 •
IGLOO nano FPGAs Package Sizes Dimensions
Packages
Length × Width (mm\mm)
Nominal Area (mm
2
)
Pitch (mm)
Height (mm)
UC36
3x3
9
0.4
0.80
UC81
4x4
16
0.4
0.80
CS81
5x5
25
0.5
0.80
QN48
6x6
36
0.4
0.90
QN68
8x8
64
0.4
0.90
VQ100
14 x 14
196
0.5
1.20
II
R evis i o n 19
IGLOO nano Low Power Flash FPGAs
IGLOO nano Device Status
IGLOO nano Devices
AGLN010
AGLN015
AGLN020
AGLN060
AGLN125
AGLN250
Status
Production
Not recommended for new designs.
Production
AGLN030Z
Production
Production
Production
AGLN060Z
AGLN125Z
AGLN250Z
Not recommended for new designs.
Not recommended for new designs.
Not recommended for new designs.
Not recommended for new designs.
IGLOO nano-Z Devices
Status
R ev i si o n 1 9
III
IGLOO nano Ordering Information
AGLN250
V2
_
Z
VQ
G
100
Y
I
Application (Temperature Range)
Blank = Enhanced Commercial (
–
20°C to +85°C Junction Temperature)
I = Industrial (
–
40°C to +100°C Junction Temperature)
PP = Pre-Production
ES = Engineering Sample (Room Temperature Only)
Security Feature
Y = Device Includes License to Implement IP Based on the
Cryptography Research, Inc. (CRI) Patent Portfolio
Blank = Device Does Not Include License to Implement IP Based
on the Cryptography Research, Inc. (CRI) Patent Portfolio
Note:
Only devices with packages greater than or equal to 5x5 are supported.
Package Lead Count
Lead-Free Packaging
Blank = Standard Packaging
G= RoHS-Compliant Packaging
Package Type
UC = Micro Chip Scale Package (0.4 mm pitch)
CS = Chip Scale Package (0.5 mm pitch)
QN = Quad Flat Pack No Leads (0.4 mm and 0.5 mm pitches)
VQ = Very Thin Quad Flat Pack (0.5 mm pitch)
DIELOT = Known Good Die
Z = nano devices without enhanced features
1
Blank = Standard
Supply Voltage
2 = 1.2 V to 1.5 V
5 = 1.5 V only
Part Number
IGLOO nano Devices
AGLN010 = 10,000 System Gates
AGLN015 = 15,000 System Gates (AGLN015 is not recommended for new designs)
AGLN020 = 20,000 System Gates
AGLN030 = 30,000 System Gates
AGLN060 = 60,000 System Gates
AGLN125 = 125,000 System Gates
AGLN250 = 250,000 System Gates
Notes:
1. Z-feature grade devices AGLN060Z, AGLN125Z, and AGLN250Z do not support the enhanced nano features of Schmitt Trigger
input, bus hold (hold previous I/O state in Flash*Freeze mode), cold-sparing, hot-swap I/O capability and 1.2 V programming.
The AGLN030 Z feature grade does not support Schmitt trigger input, bus hold and 1.2 V programming. For the VQ100, CS81,
UC81, QN68, and QN48 packages, the Z feature grade and the N part number are not marked on the device. Z feature grade
devices are not recommended for new designs.
2. AGLN030 is available in the Z feature grade only.
3. Marking Information: IGLOO nano V2 devices do not have a V2 marking, but IGLOO nano V5 devices are marked with a V5
designator.
Devices Not Recommended For New Designs
AGLN015, AGLN030Z, AGLN060Z, AGLN125Z, and AGLN250Z are not recommended for new designs. For more information on
obsoleted devices/packages, refer to the
PDN1503 - IGLOO nano Z and ProASIC3 nano Z Families.
IV
Revision 19
IGLOO nano Low Power Flash FPGAs
Device Marking
Microsemi normally topside marks the full ordering part number on each device. There are some exceptions to this, such as some of
the Z feature grade nano devices, the V2 designator for IGLOO devices, and packages where space is physically limited. Packages
that have limited characters available are UC36, UC81, CS81, QN48, QN68, and QFN132. On these specific packages, a subset of
the device marking will be used that includes the required legal information and as much of the part number as allowed by character
limitation of the device. In this case, devices will have a truncated device marking and may exclude the applications markings, such
as the I designator for Industrial Devices or the ES designator for Engineering Samples.
Figure 1
shows an example of device marking based on the AGLN250V2-CSG81. The actual mark will vary by the device/package
combination ordered.
Device Name
(seven characters)
Package
ACTEL
AGLN250
CSG81 YYWW
XXXXXXXX
X
XXX
Date Code
Wafer Lot #
Product Temperature
Grade
Country of Origin
Figure 1 •
Example of Device Marking for Small Form Factor Packages
R ev i si o n 1 9
V
DSP 与 ARM 处理器
