Advance v0.4
IGLOO nano Low-Power Flash FPGAs
with Flash*Freeze Technology
Features and Benefits
Low Power
nanoPower Consumption—Industry’s Lowest Power
1.2 V to 1.5 V Core Voltage Support for Low Power
Supports Single-Voltage System Operation
Low-Power Active FPGA Operation
Flash*Freeze Technology Enables Ultra-Low Power
Consumption while Maintaining FPGA Content
• Easy Entry to / Exit from Ultra-Low-Power Flash*Freeze
Mode
•
•
•
•
•
®
Advanced I/Os
• 1.2 V, 1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation
• Bank-Selectable I/O Voltages—up to 4 Banks per Chip
• Single-Ended I/O Standards: LVTTL, LVCMOS
3.3 V / 2.5 V / 1.8 V / 1.5 V / 1.2 V
• Wide Range Power Supply Voltage Support per JESD8-B,
Allowing I/Os to Operate from 2.7 V to 3.6 V
• Wide Range Power Supply Voltage Support per JESD8-12,
Allowing I/Os to Operate from 1.14 V to 1.575 V
• I/O Registers on Input, Output, and Enable Paths
• Selectable Schmitt Trigger Inputs
• Hot-Swappable and Cold-Sparing I/Os
• Programmable Output Slew Rate and Drive Strength
• Weak Pull-Up/-Down
• IEEE 1149.1 (JTAG) Boundary Scan Test
• Pin-Compatible Packages across the IGLOO Family
†
• Up to Six CCC Blocks, One with an Integrated PLL
• Configurable Phase Shift, Multiply/Divide, Delay
Capabilities, and External Feedback
• Wide Input Frequency Range (1.5 MHz up to 250 MHz)
Small Footprint Packages
• As Small as 3x3 mm in Size
Wide Range of Features
• 10 k to 250 k System Gates
• Up to 36 kbits of True Dual-Port SRAM
• Up to 71 User I/Os
Reprogrammable Flash Technology
•
•
•
•
130-nm, 7-Layer Metal, Flash-Based CMOS Process
Live-at-Power-Up (LAPU) Level 0 Support
Single-Chip Solution
Retains Programmed Design When Powered Off
Clock Conditioning Circuit (CCC) and PLL
In-System Programming (ISP) and Security
• Secure ISP Using On-Chip 128-Bit Advanced Encryption
Standard (AES) Decryption via JTAG (IEEE 1532–compliant)
• FlashLock
®
to Secure FPGA Contents
Embedded Memory
• 1 kbit of FlashROM User Nonvolatile Memory
• SRAMs and FIFOs with Variable-Aspect-Ratio 4,608-Bit RAM
Blocks (×1, ×2, ×4, ×9, and ×18 organizations)
†
• True Dual-Port SRAM (except × 18 organization)
†
High-Performance Routing Hierarchy
• Segmented, Hierarchical Routing and Clock Structure
Enhanced Commercial Temperature Range
• –20°C to +70°C
IGLOO nano Devices
IGLOO nano Devices
System Gates
Typical Equivalent Macrocells
VersaTiles (D-flip-flops)
Flash*Freeze Mode (typical, µW)
RAM kbits (1,024
4,608-Bit Blocks
FlashROM Bits
Secure (AES) ISP
VersaNet
I/O Banks
Maximum User I/Os
Maximum User I/Os (Known Good Die)
Package Pins
UC/CS
QFN
VQFP
2
2
AGLN010
10 k
86
260
2
–
–
1k
–
–
4
2
34
34
UC36
QN48
AGLN015
15 k
128
384
4
–
–
1k
–
–
4
3
49
–
AGLN020
20 k
172
520
4
–
–
1k
–
–
4
3
52
52
AGLN030
1
30 k
256
768
5
–
–
1k
–
–
6
2
81
83
AGLN060
60 k
512
1,536
10
18
4
1k
Yes
1
18
2
71
71
CS81
QN100
VQ100
AGLN125
125 k
1,024
3,072
16
36
8
1k
Yes
1
18
2
71
71
CS81
QN100
VQ100
AGLN250
250 k
2,048
6,144
24
36
8
1k
Yes
1
18
4
68
68
CS81
QN100
VQ100
bits)
2
Integrated PLL in CCCs
2
Globals
3
QN68
UC81, CS81 UC81, CS81
QN68
QN48, QN68
VQ100
Notes:
1. AGLN030 is available in the Z feature grade only and offers package compatibility with the lower density nano devices. Refer
to
"IGLOO nano Ordering Information" on page III.
2. AGLN060, AGLN125, and AGLN250 in the CS81 package do not support PLLs. AGLN030 and smaller devices do not support this
feature
.
3. Six chip (main) and three quadrant global networks are available for AGLN060 and above.
4. For higher densities and support of additional features, refer to the
IGLOO
and
IGLOOe
handbooks.
† AGLN030 and smaller devices do not support this feature.
December 2008
© 2008 Actel Corporation
I
IGLOO nano Low-Power Flash FPGAs
I/Os Per Package
IGLOO nano Devices
Known Good Die
UC36
QN48
QN68
UC81
CS81
QN100
VQ100
Notes:
1. AGLN030 is available in the Z feature grade only and offers package compatibility with the lower density nano devices.
Refer to
"IGLOO nano Ordering Information" on page III
.
2. When considering migrating your design to a lower- or higher-density device, refer to the
IGLOO Handbook
to ensure
compliance with design and board migration requirements.
3. When the Flash*Freeze pin is used to directly enable Flash*Freeze mode and not used as a regular I/O, the number of single-
ended user I/Os available is reduced by one.
4. "G" indicates RoHS-compliant packages. Refer to
"IGLOO nano Ordering Information" on page III
for the location of the "G"
in the part number. For nano devices, the VQ100 package is offered in both leaded and RoHS-compliant versions. All other
packages are RoHS-compliant only.
AGLN010
34
23
34
AGLN015
–
AGLN020
52
AGLN030
1
83
AGLN060
71
AGLN125
71
AGLN250
68
34
49
49
52
52
49
66
66
60
71
77
71
60
71
71
60
68
68
IGLOO FPGAs Package Sizes Dimensions
Packages
Length × Width (mm\mm)
Nominal Area (mm
2
)
Pitch (mm)
Height (mm)
UC36
3x3
9
0.4
0.80
UC81
4x4
16
0.4
0.80
CS81
5x5
36
0.5
0.80
QN48
6x6
36
0.4
0.90
QN68
8x8
64
0.4
0.90
QN100
8x8
64
0.5
0.85
VQ100
14 x 14
196
0.5
1.20
II
A d v a n c e v 0 .4
IGLOO nano Low-Power Flash FPGAs
IGLOO nano Ordering Information
AGLN250
V2
_
Z
VQ
G
100
I
Application (Temperature Range)
Blank =
Commercial
(
–
20°C to +70°C Ambient Temperature)
I = Industrial (
–
40°C to +85°C Ambient Temperature)
PP = Pre-Production
ES = Engineering
Sample
(Room Temperature Only)
Package Lead
Count
Lead-Free Packaging
Blank =
Standard
Packaging
G=
RoHS-Compliant Packaging
Package Type
UC = Micro
Chip Scale
Package (0.4 mm pitch)
CS
=
Chip Scale
Package (0.5 mm pitch)
QN = Quad Flat Pack No Leads (0.4 mm and 0.5 mm pitches)
VQ = Very Thin Quad Flat Pack (0.5 mm pitch)
DIELOT = Known
Good
Die
Speed Grade
F = 20%
Slower
than
Standard
2
Blank =
Standard
Feature
Grade
Z = nano
devices
without enhanced features
3
Blank =
Standard
Supply
Voltage
2 = 1.2 V to 1.5 V
5 = 1.5 V only
Part Number
IGLOO nano Devices
AGLN010 = 10,000
System Gates
AGLN015 = 15,000
System Gates
AGLN020 = 20,000
System Gates
AGLN030 = 30,000
System Gates
AGLN060 =
60,000 System Gates
AGLN125 = 125,000
System Gates
AGLN250 = 250,000
System Gates
Notes:
1. Marking Information: IGLOO nano V2 devices do not have V2 marking, but IGLOO nano V5 devices are marked with a V5
designator.
2. The DC and switching characteristics for the –F speed grade targets are based only on simulation. The characteristics provided for
the –F speed grade are subject to change after establishing FPGA specifications. Some restrictions might be added and will be
reflected in future revisions of this document. The –F speed grade is only supported in the commercial temperature range.
3. For the AGLN060, AGLN125, and AGLN250, the Z feature grade does not support the enhanced nano features of Schmitt trigger
input, bus hold, cold-sparing, and hot-swap I/O capability. The AGLN030 Z feature grade does not support Schmitt trigger input
and bus hold. For the VQ100, CS81, UC81, QN68, and QN48 packages, the Z feature grade and the N part number are not marked
on the device.
Advance v0.4
III
IGLOO nano Low-Power Flash FPGAs
IGLOO nano Product Available in the Z Feature Grade
Devices
Packages
AGLN030
QN48
QN68
UC81
CS81
–
VQ100
AGLN060
–
–
–
CS81
QN100
VQ100
AGLN125
–
–
–
CS81
QN100
VQ100
AGLN250
–
–
–
–
–
VQ100
Temperature Grade Offerings
Package
UC36
QN48
QN68
UC81
CS81
QN100
VQ100
Notes:
1. C = Commercial temperature range: –20°C to 70°C ambient temperature.
2. I = Industrial temperature range: –40°C to 85°C ambient temperature.
AGLN010
C, I
C, I
–
–
–
–
–
AGLN015
–
–
C, I
–
–
–
–
AGLN020
–
–
C, I
C, I
C, I
–
–
AGLN030
–
C, I
C, I
C, I
C, I
–
C, I
AGLN060
–
–
–
–
C, I
C, I
C, I
AGLN125
–
–
–
–
C, I
C, I
C, I
AGLN250
–
–
–
–
C, I
C, I
C, I
Speed Grade and Temperature Grade Matrix
Temperature Grade
C
2
I
3
Notes:
1. The characteristics provided for the –F speed grade are subject to change after establishing FPGA specifications. Some
restrictions might be added and will be reflected in future revisions of this document. The –F speed grade is supported
only in the commercial temperature range.
2. C = Commercial temperature range: –20°C to 70°C ambient temperature.
3. I = Industrial temperature range: –40°C to 85°C ambient temperature.
–F
1
Std.
✓
–
✓
✓
Contact your local Actel representative for device availability:
http://www.actel.com/contact/default.aspx.
IV
A d v a n c e v 0 .4
1 – IGLOO nano Device Overview
General Description
The IGLOO family of flash FPGAs, based on a 130-nm flash process, offers the lowest power FPGA, a
single-chip solution, small footprint packages, reprogrammability, and an abundance of advanced
features.
The Flash*Freeze technology used in IGLOO nano devices enables entering and exiting an ultra-
low-power mode that consumes nanoPower while retaining SRAM and register data. Flash*Freeze
technology simplifies power management through I/O and clock management with rapid recovery
to operation mode.
The Low Power Active capability (static idle) allows for ultra-low-power consumption while the
IGLOO nano device is completely functional in the system. This allows the IGLOO nano device to
control system power management based on external inputs (e.g., scanning for keyboard stimulus)
while consuming minimal power.
Nonvolatile flash technology gives IGLOO nano devices the advantage of being a secure, low-
power, single-chip solution that is live at power-up (LAPU). The IGLOO nano device is
reprogrammable and offers time-to-market benefits at an ASIC-level unit cost.
These features enable designers to create high-density systems using existing ASIC or FPGA design
flows and tools.
IGLOO nano devices offer 1 kbit of on-chip, reprogrammable, nonvolatile FlashROM storage as well
as clock conditioning circuitry based on an integrated phase-locked loop (PLL). The AGLN030 and
smaller devices have no PLL or RAM support. IGLOO nano devices have up to 250 k system gates,
supported with up to 36 kbits of true dual-port SRAM and up to 71 user I/Os.
IGLOO nano devices increase the breadth of the IGLOO product line by adding new features and
packages for greater customer value in high volume consumer, portable, and battery-backed
markets. Features such as smaller footprint packages designed with two-layer PCBs in mind, power
consumption measured in nanoPower, Schmitt trigger, and bus hold functionality make these
devices ideal for deployment in applications that require high levels of flexibility and low cost.
Flash*Freeze Technology
The IGLOO nano device offers unique Flash*Freeze technology, allowing the device to enter and
exit ultra-low-power Flash*Freeze mode. IGLOO nano devices do not need additional components
to turn off I/Os or clocks while retaining the design information, SRAM content, and registers.
Flash*Freeze technology is combined with in-system programmability, which enables users to
quickly and easily upgrade and update their designs in the final stages of manufacturing or in the
field. The ability of IGLOO nano V2 devices to support a wide range of core voltage (1.2 V to 1.5 V)
allows further reduction in power consumption, thus achieving the lowest total system power.
During Flash*Freeze mode, each I/O can be set to the following configurations: hold previous state,
tristate, HIGH, or LOW.
The availability of low-power modes, combined with reprogrammability, a single-chip and single-
voltage solution, and small-footprint packages make IGLOO nano devices the best fit for portable
electronics.
A dv a n c e v 0. 4
1-1
