[AK4426]
= Preliminary =
AK4426
192kHz 24-Bit Stereo
ΔΣ
DAC with 2Vrms Output
GENERAL DESCRIPTION
The AK4426 is a 5V 24-bit stereo DAC with an integrated 2Vrms output buffer. A charge pump in the
buffer develops an internal negative power supply rail that enables a ground-referenced 2Vrms output.
Using AKM’s multi bit modulator architecture, the AK4426 delivers a wide dynamic range while preserving
linearity for improved THD+N performance. The AK4426 integrates a combination of switched-capacitor
and continuous-time filters, increasing performance for systems with excessive clock jitter. The 24-bit
word length and 192kHz sampling rate make this part ideal for a wide range of consumer audio
applications, such as DVD, AV receiver system and set-top boxes. The AK4426 is offered in a space
saving 16pin TSSOP package.
FEATURES
Sampling Rate Ranging from 8kHz to 192kHz
128 times Oversampling (Normal Speed Mode)
64 times Oversampling (Double Speed Mode)
32 times Oversampling (Quad Speed Mode)
24-Bit 8 times FIR Digital Filter
Switched-Capacitor Filter with High Tolerance to Clock Jitter
Single Ended 2Vrms Output Buffer
Digital De-emphasis Filter: 32kHz, 44.1kHz or 48kHz
Soft mute
Digital Attenuator (Linear 256 Step)
Control I/F: I
2
C-Bus
Audio I/F format: 24Bit MSB justified, 24/20/16 LSB justified or
I
2
S compatible
Master clock: 512fs, 768fs or 1152fs (Normal Speed Mode)
256fs or 384fs (Double Speed Mode)
128fs, 192fs (Quad Speed Mode)
THD+N: -91dB
Dynamic Range: 106dB
Automatic Power-on Reset Circuit
Power supply: +4.5
∼
+5.5V
Ta = -20 to 85°C (ET), -40 to 85
°C
(VT)
Small Package: 16pin TSSOP (6.4mm x 5.0mm)
Rev.0.3
-1-
2009/12
[AK4426]
MCLK
AVDD
CAD0
SCL
SDA
Control
Interface
De-emphasis
Control
Clock
Divider
VSS2
LRCK
BICK
SDTI
Audio
Data
Interface
8X
Interpolator
8X
Interpolator
Charge
Pump
CP
CN
ΔΣ
Modulator
ΔΣ
Modulator
SCF
LPF
SCF
LPF
AOUTL
AOUTR
VEE
VSS1
VDD
1μ
1μ
Block Diagram
Rev.0.3
-2-
2009/12
[AK4426]
■
Ordering Guide
AK4426ET
AK4426VT
AKD4426
-20
∼
+85°C
16pin TSSOP (0.65mm pitch)
-40
∼
+85°C
16pin TSSOP (0.65mm pitch)
Evaluation Board for AK4426
■
Pin Layout
VDD
MCLK
BICK
SDTI
LRCK
CAD0
SCL
SDA
1
2
3
4
5
6
7
8
16
15
14
VSS1
CP
CN
VEE
AOUTL
VSS2
AVDD
AOUTR
AK4426
Top
View
13
12
11
10
9
Rev.0.3
-3-
2009/12
[AK4426]
PIN/FUNCTION
Function
Digital Circuit and Charge Pump Circuit Power Supply Pin: 4.5V∼5.5V
Master Clock Input Pin
2
MCLK
I
An external TTL clock must be input on this pin.
3
Audio Serial Data Clock Pin
BICK
I
4
Audio Serial Data Input Pin
SDTI
I
5
L/R Clock Pin
LRCK
I
6
Chip Address 0bit
CAD0
I
7
Control Clock input Pin
SCL
I
8
Control Data Input/Output pin
SDA
I/O
Rch Analog Output Pin
9
AOUTR
O
When power down, outputs VSS(0V, typ).
10
Analog Block Power Supply Pin: 4.5V∼5.5V
AVDD
-
11
Ground Pin2
VSS2
-
Lch Analog Output Pin
12
AOUTL
O
When power down, outputs VSS(0V, typ).
Negative Voltage Output Pin
Connect to VSS1 with a 1.0μF capacitor which is low ESR (Equivalent
13
Series Resistance) over all temperature range. When this capacitor has the
VEE
O
polarity, the positive polarity pin must be connected to the VSS1 pin. Non
polarity capacitors can also be used.
Negative Charge Pump Capacitor Terminal Pin
Connect to CP with a 1.0μF capacitor which is low ESR (Equivalent Series
14
Resistance) over all temperature range. When this capacitor has the polarity,
CN
I
the positive polarity pin must be connected to the CP pin. Non polarity
capacitors can also be used.
Positive Charge Pump Capacitor Terminal Pin
Connect to CN with a 1.0μF capacitor which is low ESR (Equivalent Series
15
Resistance) over all temperature range. When this capacitor has the polarity,
CP
I
the positive polarity pin must be connected to the CP pin. Non polarity
capacitors can also be used.
16
Ground Pin1
VSS1
-
Note: All input pins except for the CN pin should not be left floating.
No.
1
Pin Name
VDD
I/O
-
Rev.0.3
-4-
2009/12
[AK4426]
ABSOLUTE MAXIMUM RATINGS
(VSS1=VSS2=0V;
Note 1)
Parameter
Power Supply
Input Current (any pins except for supplies)
Input Voltage
AK4426ET
Ambient Operating Temperature
AK4426VT
Storage Temperature
Note 1. All voltages with respect to ground.
Note 2. VSS1, VSS2 connect to the same analog ground.
Symbol
VDD
CVDD
IIN
VIND
Ta
Ta
Tstg
min
-0.3
-0.3
-
-0.3
-20
-40
-65
max
+6.0
+6.0
±10
VDD+0.3
85
85
150
Units
V
V
mA
V
°C
°C
°C
WARNING: Operation at or beyond these limits may result in permanent damage to the device.
Normal operation is not guaranteed at these extremes.
RECOMMENDED OPERATING CONDITIONS
(VSS1=VSS2=0V;
Note 1)
Parameter
Power Supply
Note 3. AVDD should be equal to VDD
*AKM assumes no responsibility for the usage beyond the conditions in this datasheet.
Symbol
VDD
AVDD
min
+4.5
typ
+5.0
VDD
max
+5.5
Units
V
Rev.0.3
-5-
2009/12
