CERAMIC SMD CRYSTAL CLOCK OSCILLATOR
WITH VOLTAGE CONTROL
ALVD SERIES
: PRELIMINARY
APPLICATIONS:
• SONET, xDSL
• SDH, CPE
• STB
FEATURES:
• Based on a proprietary digital multiplier
• 2.5V to 3.3V +/- 5% operation
• Tri-State Output
• Ceramic SMD, low profile package
• Low Phase Jitter
• 155.52MHz, 311.04MHz, and 622.08MHz applications
5.08 x 7.0 x 1.8mm
| | | | | | | | | | | | | | |
STANDARD SPECIFICATIONS:
PARAMETERS
Frequency Range
Operating Temperature
Storage Temperature
Overall Frequency Stability
Supply Voltage (Vdd)
Voltage Control (Vc)
Frequency Pullability
Linearity
Jitter (12KHz - 20MHz)
Phase Noise
750 KHz to 800 MHz
0°C to + 70°C (see options)
- 55°C to + 125°C
± 50 ppm max. (see options)
2.5V to 3.3 Vdc ± 5%
0.3V
DC
min, 1.65V
DC
typ, 3.0V
DC
max
± 100 ppm
5% typ, 10% max.
RMS phase jitter 3pS typ. < 5pS max. period jitter < 35pS peak to peak
-109 dBc/Hz @ 1kHz Offset from 622.08MHz
-110 dBc/Hz @ 10kHz Offset from 622.08MHz
-109 dBc/Hz @ 100kHz Offset from 622.08MHz
“1” (V
IH
> 0.7*V
DD
) or open: Oscillation/ “0” (V
IH
> 0.3*V
DD
) No Oscillation/Hi Z
65mA (Fo < 96MHz), 100mA (Fo < 700.00MHz)
45% min, 50% typical, 55% max.
V
DD
-1.025V min, V
DD
-0.880V max.
V
DD
-1.810V min, V
DD
-1.620V max.
0.6nSec typical, 1.5ns max
0.6nSec typical, 1.5ns max
1.2ns typical, 1.6ns max
45% min, 50% typical, 55% max
45mA max (Fo < 96MHz), 80mA max (Fo < 700MHz)
45% min, 50% typical, 55% max
247mV min, 355mV typical, 454mV max
-50mV min, 50mV max
V
OH
= 1.4V typical, 1.6V max
V
OL
= 0.9V min, 1.1V typical
V
OS
= 1.125V min, 1.2V typical, 1.375V max
∆V
OS
= 0mV min, 3mV typical, 25mV max
±1µA typical, ±10µA max
0.2ns min, 0.7ns typical, 1.0ns max
0.2ns min, 0.7ns typical, 1.0ns max
Tri-State Function
PECL
Supply Current (I
DD
)
Symmetry (Duty Cycle)
Output Logic High
Output Logic Low
Clock Rise time (t
r
) @ 20/80%
Clock Fall time (t
f
) @ 80/20%
CMOS
Output Clock Rise/ Fall Time [10%~90% VDD with 10pF load]
Output Clock Duty Cycle [Measured @ 50% VDD]
LVDS
Supply Current (I
DD
) [Fout = 212.50MHz]
Output Clock Duty Cycle @ 1.25V
Output Differential Voltage (V
OD
)
VDD Magnitude Change (∆V
OD
)
Output High Voltage
Output Low Voltage
Offset Voltage [R
L
= 100Ω]
Offset Magnitude Voltage[RL = 100Ω]
Power-off Leakage (I
OXD
) [Vout=VDD or GND, VDD=0V]
Differential Clock Rise Time (t
r
) [R
L
=100Ω, CL=10pF]
Differential Clock Fall Time (t
f
) [R
L
=100Ω, CL=10pF]
ABRACON IS
ISO 9001 / QS 9000
CERTIFIED
rev2.1-8/05
30332 Esperanza, Rancho Santa Margarita, California 92688
tel 949-546-8000
|
fax 949-546-8001
| www.abracon.com
CERAMIC SMD CRYSTAL CLOCK OSCILLATOR
WITH VOLTAGE CONTROL
ALVD SERIES
: PRELIMINARY
5.08 x 7.0 x 1.8mm
| | | | | | | | | | | | | | |
PIN ASSIGNMENTS:
PIN #
1
2
3
4
5
6
NAME
Tri-state or VC
Tri-state or NC
GND
Q
Q
V
DD
DESCRIPTION
Tri-state or Voltage Control
Tri-state or No Connect
Ground
PECL, LVDS, or CMOS Output
Complimentary PECL,LVDS, or NC
VDD Connection
TRI-STATE PIN OPERATION:
OUTPUT TYPE
PECL
(P)
LVDS & CMOS
(L, C)
PECL
(P)
PIN 2 LOGIC LEVEL*
0 (Default)
1
0
1(Default)
0
1(Default)
OUTPUT STATE
Enabled
Tri-state
Tri-state
Enabled
Disabled
Enabled
*Connect to VDD from logic level "1", connect to ground for logic level "0".
MARKING:
- TUH
(Frequency: T=First “”10” digit of frequency, U=First “unit” of frequency,
H=First “tenth” of frequency, Ex: 100 for 10.0MHz)
- ALVD ZYX (Z: Month, A to L; Y: Year, 5 for 2005; X: Traceability Code)
OUTLINE DRAWING:
OPTIONS AND PART IDENTIFICATION (Left blank if standard):
ALVD - Frequency - Temperature - Frequency Stability - Pulling - Output Type
Temperature:
D
for -10°C to +60°C
E
for -20°C to +70°C
F
for -30°C to +70°C
N
for -30°C to +85°C
L
for -40°C to +85°C
Stability options:
R
for ± 25 ppm
K
for ± 30 ppm
H
for ± 35 ppm
Pulling options:
N
15 ± 150 ppm min.
Output option:
P
= PECL
P1
= PECL1
L
= LVDS
C
= CMOS
Dimensions: inch (mm)
ABRACON IS
ISO 9001 / QS 9000
CERTIFIED
rev2.1-8/05
30332 Esperanza, Rancho Santa Margarita, California 92688
tel 949-546-8000
|
fax 949-546-8001
| www.abracon.com
