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AM27X2048-90PI

2 Megabit (128 K x 16-bit) cmos expressrom device

器件类别:存储    存储   

厂商名称:AMD(超微)

厂商官网:http://www.amd.com

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器件参数
参数名称
属性值
是否Rohs认证
不符合
厂商名称
AMD(超微)
零件包装代码
DIP
包装说明
DIP, DIP40,.6
针数
40
Reach Compliance Code
unknown
ECCN代码
EAR99
最长访问时间
90 ns
JESD-30 代码
R-PDIP-T40
JESD-609代码
e0
内存密度
2097152 bit
内存集成电路类型
MASK ROM
内存宽度
16
功能数量
1
端子数量
40
字数
131072 words
字数代码
128000
工作模式
ASYNCHRONOUS
最高工作温度
85 °C
最低工作温度
-40 °C
组织
128KX16
输出特性
3-STATE
封装主体材料
PLASTIC/EPOXY
封装代码
DIP
封装等效代码
DIP40,.6
封装形状
RECTANGULAR
封装形式
IN-LINE
并行/串行
PARALLEL
峰值回流温度(摄氏度)
NOT SPECIFIED
电源
5 V
认证状态
Not Qualified
最大待机电流
0.0001 A
最大压摆率
0.05 mA
最大供电电压 (Vsup)
5.5 V
最小供电电压 (Vsup)
4.5 V
标称供电电压 (Vsup)
5 V
表面贴装
NO
技术
CMOS
温度等级
INDUSTRIAL
端子面层
Tin/Lead (Sn/Pb)
端子形式
THROUGH-HOLE
端子节距
2.54 mm
端子位置
DUAL
处于峰值回流温度下的最长时间
NOT SPECIFIED
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FINAL
Am27X2048
2 Megabit (128 K x 16-Bit) CMOS ExpressROM Device
DISTINCTIVE CHARACTERISTICS
s
As an OTP EPROM alternative:
— Factory optimized programming
— Fully tested and guaranteed
s
As a Mask ROM alternative:
— Shorter leadtime
— Lower volume per code
s
Fast access time
— 70 ns
s
Single +5 V power supply
s
Compatible with JEDEC-approved EPROM
pinout
s
±10%
power supply tolerance
s
High noise immunity
s
Low power dissipation
— 100 µA maximum CMOS standby current
s
Available in Plastic Dual-In-line Package (PDIP)
and Plastic Leaded Chip Carrier (PLCC)
s
Latch-up protected to 100 mA from –1 V to
V
CC
+ 1 V
s
Versatile features for simple interfacing
— Both CMOS and TTL input/output compatibility
— Two line control functions
GENERAL DESCRIPTION
The Am27X2048 is a factory programmed and tested
OTP EPROM. It is programmed after packaging prior to
final test. Every device is rigorously tested under AC
and DC operating conditions to your stable code. It is
organized as 128 Kwords by 16 bits per word and is
available in plastic dual in-line packages (PDIP), as
well as plastic leaded chip carrier (PLCC) packages.
ExpressROM devices provide a board-ready memory
solution for medium to high volume codes with short
leadtimes. This offers manufacturers a cost-effective
and flexible alternative to OTP EPROMs and mask pro-
grammed ROMs.
Data can be accessed as fast as 70 ns, allowing
high-performance microprocessors to operate with re-
duced WAIT states. The device offers separate Output
Enable (OE#) and Chip Enable (CE#) controls, thus
eliminating bus contention in a multiple bus micropro-
cessor system.
AMD’s CMOS process technology provides high
speed, low power, and high noise immunity. Typical
power consumption is only 125 mW in active mode,
and 100 µW in standby mode.
BLOCK DIAGRAM
V
CC
V
SS
OE#
CE#
Output Enable
Chip Enable
and
Prog Logic
Y
Decoder
A0–A16
Address
Inputs
Output
Buffers
Data Outputs DQ0–DQ15
Y
Gating
X
Decoder
2,097,152
Bit Cell
Matrix
15653D-1
Publication#
15653
Rev:
D
Amendment/0
Issue Date:
May 1998
PRODUCT SELECTOR GUIDE
Family Part Number
Speed Options
Max Access Time (ns)
CE# (E#) Access (ns)
OE# (G#) Access (ns)
V
CC
= 5.0 V
±
5%
V
CC
= 5.0 V
±
10%
-70
70
70
40
-90
90
90
40
-120
120
120
50
-150
150
150
65
-200
200
200
75
250
250
75
Am27X2048
-255
CONNECTION DIAGRAMS
DIP
V
PP
CE# (E#)
DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
DQ9
DQ8
V
SS
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
OE# (G#)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
V
CC
A16
A15
A14
A13
A12
A11
A10
A9
V
SS
A8
A7
A6
A5
A4
A3
A2
A1
A0
15653D-2
PLCC
DU (Note 2)
PGM# (P#)
V
CC
A16
A15
6
DQ12
DQ11
DQ10
DQ9
DQ8
V
SS
NC
DQ7
DQ6
DQ5
DQ4
7
8
9
10
11
12
13
14
15
16
5
4
3
2
1 44 43 42 41 40
39
38
37
36
35
34
33
32
31
30
A13
A12
A11
A10
A9
V
SS
NC
A8
A7
A6
A5
29
17
18 19 20 21 22 23 24 25 26 27 28
DQ3
DQ2
DQ1
DQ0
A0
A1
A2
A3
OE# (G#)
DU (Note 2)
A4
A14
15653D-3
Notes:
1. JEDEC nomenclature is in parenthesis.
2. Don’t use (DU) for PLCC.
PIN DESIGNATIONS
A0–A16
CE# (E#)
= Address Inputs
= Chip Enable Input
LOGIC SYMBOL
17
A0–A16
DQ0–DQ15
CE# (E#)
16
DQ0–DQ15 = Data Input/Outputs
OE# (G#)
PGM# (P#)
V
CC
V
PP
V
SS
NC
= Output Enable Input
= Program Enable Input
= V
CC
Supply Voltage
= Program Voltage Input
= Ground
= No Internal Connection
OE# (G#)
15653D-4
2
Am27X2048
V
PP
PGM# (P#)
CE (E)
DQ13
DQ14
DQ15
ORDERING INFORMATION
Standard Products
AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed
by a combination of the following:
AM27X2048
-70
J
C
XXXXX
CODE DESIGNATION
Assigned by AMD
TEMPERATURE RANGE
C = Commercial (0°C to +70
°
C)
I = Industrial (–40
°
C to +85
°
C)
PACKAGE TYPE
P = 40-Pin Plastic Dual In-Line Package (PD 040)
J = 44-Pin Plastic Leaded Chip Carrier (PL 044)
SPEED OPTION
See Product Selector Guide and Valid Combinations
DEVICE NUMBER/DESCRIPTION
Am27X2048
2 Megabit (128 K x 16-Bit) CMOS ExpressROM Device
Valid Combinations
AM27X2048-70
AM27X2048-90
AM27X2048-120
AM27X2048-150
AM27X2048-200
AM27X2048-255
V
CC
= 5.0 V
±
5%
PC, JC, PI, JI
Valid Combinations
Valid Combinations list configurations planned to be sup-
ported in volume for this device. Consult the local AMD sales
office to confirm availability of specific valid combinations and
to check on newly released combinations.
Am27X2048
3
FUNCTIONAL DESCRIPTION
Read Mode
To obtain data at the device outputs, Chip Enable (CE#)
and Output Enable (OE#) must be driven low. CE# con-
trols the power to the device and is typically used to se-
lect the device. OE# enables the device to output data,
independent of device selection. Addresses must be
stable for at least t
ACC
–t
OE
. Refer to the Switching
Waveforms section for the timing diagram.
CE# should be decoded and used as the primary de-
vice-selecting function, while OE# be made a common
connection to all devices in the array and connected to
the READ line from the system control bus. This as-
sures that all deselected memory devices are in their
low-power standby mode and that the output pins are
only active when data is desired from a particular mem-
ory device.
Standby Mode
The device enters the CMOS standby mode when CE#
is at V
CC
±
0.3 V. Maximum V
CC
current is reduced to
100 µA. The device enters the TTL-standby mode
when CE# is at V
IH
. Maximum V
CC
current is reduced
to 1.0 mA. When in either standby mode, the device
places its outputs in a high-impedance state, indepen-
dent of the OE# input.
System Applications
During the switch between active and standby condi-
tions, transient current peaks are produced on the ris-
ing and falling edges of Chip Enable. The magnitude of
these transient current peaks is dependent on the out-
put capacitance loading of the device. At a minimum, a
0.1 µF ceramic capacitor (high frequency, low inherent
inductance) should be used on each device between
V
CC
and V
SS
to minimize transient effects. In addition,
to overcome the voltage drop caused by the inductive
effects of the printed circuit board traces on Express-
ROM device arrays, a 4.7 µF bulk electrolytic capacitor
should be used between V
CC
and V
SS
for each eight
devices. The location of the capacitor should be close
to where the power supply is connected to the array.
Output OR-Tieing
To accommodate multiple memory connections, a
two-line control function provides:
s
Low memory power dissipation, and
s
Assurance that output bus contention will not occur.
MODE SELECT TABLE
Mode
Read
Output Disable
Standby (TTL)
Standby (CMOS)
CE#
V
IL
X
V
IH
V
CC
±
0.3 V
OE#
V
IL
V
IH
X
X
PGM#
X
X
X
X
V
PP
X
X
X
X
Outputs
D
OUT
High Z
High Z
High Z
Note:
X = Either V
IH
or V
IL
.
4
Am27X2048
ABSOLUTE MAXIMUM RATINGS
Storage Temperature
OTP Products. . . . . . . . . . . . . . . . . . –65°C to +125°C
Ambient Temperature
with Power Applied. . . . . . . . . . . . . . –55°C to +125°C
Voltage with Respect to V
SS
All pins except V
CC
. . . . . . . . . –0.6 V to V
CC
+ 0.6 V
V
CC
(Note 1). . . . . . . . . . . . . . . . . . . . . –0.6 V to 7.0 V
OPERATING RANGES
Commercial (C) Devices
Ambient Temperature (T
A
) . . . . . . . . . . .0°C to +70°C
Industrial (I) Devices
Ambient Temperature (T
A
) . . . . . . . . .–40°C to +85°C
Supply Read Voltages
V
CC
for ± 5% devices . . . . . . . . . . +4.75 V to +5.25 V
V
CC
for ± 10% devices . . . . . . . . . +4.50 V to +5.50 V
Operating ranges define those limits between which the func-
tionality of the device is guaranteed.
Note:
1. Minimum DC voltage on input or I/O pins –0.5 V. During
voltage transitions, the input may overshoot V
SS
to –2.0 V
for periods of up to 20 ns. Maximum DC voltage on input
and I/O pins is V
CC
+ 5 V. During voltage transitions, input
and I/O pins may overshoot to V
CC
+ 2.0 V for periods up
to 20 ns.
Stresses above those listed under “Absolute Maximum Rat-
ings” may cause permanent damage to the device. This is a
stress rating only; functional operation of the device at these
or any other conditions above those indicated in the opera-
tional sections of this specification is not implied. Exposure of
the device to absolute maximum ratings for extended periods
may affect device reliability.
Am27X2048
5
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参数对比
与AM27X2048-90PI相近的元器件有:AM27X2048-255JI、AM27X2048-255JC、AM27X2048-90JC、AM27X2048-90PC、AM27X2048-120PC。描述及对比如下:
型号 AM27X2048-90PI AM27X2048-255JI AM27X2048-255JC AM27X2048-90JC AM27X2048-90PC AM27X2048-120PC
描述 2 Megabit (128 K x 16-bit) cmos expressrom device 2 Megabit (128 K x 16-bit) cmos expressrom device 2 Megabit (128 K x 16-bit) cmos expressrom device 2 Megabit (128 K x 16-bit) cmos expressrom device 2 Megabit (128 K x 16-bit) cmos expressrom device 2 Megabit (128 K x 16-bit) cmos expressrom device
是否Rohs认证 不符合 不符合 不符合 不符合 不符合 不符合
零件包装代码 DIP LCC LCC LCC DIP DIP
包装说明 DIP, DIP40,.6 QCCJ, LDCC44,.7SQ QCCJ, LDCC44,.7SQ QCCJ, LDCC44,.7SQ DIP, DIP40,.6 DIP, DIP40,.6
针数 40 44 44 44 40 40
Reach Compliance Code unknown unknown unknown unknown unknown unknown
ECCN代码 EAR99 EAR99 EAR99 EAR99 EAR99 EAR99
最长访问时间 90 ns 250 ns 250 ns 90 ns 90 ns 120 ns
JESD-30 代码 R-PDIP-T40 S-PQCC-J44 S-PQCC-J44 S-PQCC-J44 R-PDIP-T40 R-PDIP-T40
JESD-609代码 e0 e0 e0 e0 e0 e0
内存密度 2097152 bit 2097152 bit 2097152 bit 2097152 bit 2097152 bit 2097152 bit
内存集成电路类型 MASK ROM OTP ROM OTP ROM MASK ROM MASK ROM OTP ROM
内存宽度 16 16 16 16 16 16
功能数量 1 1 1 1 1 1
端子数量 40 44 44 44 40 40
字数 131072 words 131072 words 131072 words 131072 words 131072 words 131072 words
字数代码 128000 128000 128000 128000 128000 128000
工作模式 ASYNCHRONOUS ASYNCHRONOUS ASYNCHRONOUS ASYNCHRONOUS ASYNCHRONOUS ASYNCHRONOUS
最高工作温度 85 °C 85 °C 70 °C 70 °C 70 °C 70 °C
组织 128KX16 128KX16 128KX16 128KX16 128KX16 128KX16
输出特性 3-STATE 3-STATE 3-STATE 3-STATE 3-STATE 3-STATE
封装主体材料 PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY
封装代码 DIP QCCJ QCCJ QCCJ DIP DIP
封装等效代码 DIP40,.6 LDCC44,.7SQ LDCC44,.7SQ LDCC44,.7SQ DIP40,.6 DIP40,.6
封装形状 RECTANGULAR SQUARE SQUARE SQUARE RECTANGULAR RECTANGULAR
封装形式 IN-LINE CHIP CARRIER CHIP CARRIER CHIP CARRIER IN-LINE IN-LINE
并行/串行 PARALLEL PARALLEL PARALLEL PARALLEL PARALLEL PARALLEL
峰值回流温度(摄氏度) NOT SPECIFIED NOT SPECIFIED NOT SPECIFIED 220 NOT SPECIFIED NOT SPECIFIED
电源 5 V 5 V 5 V 5 V 5 V 5 V
认证状态 Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified
最大待机电流 0.0001 A 0.0001 A 0.0001 A 0.0001 A 0.0001 A 0.0001 A
最大压摆率 0.05 mA 0.05 mA 0.05 mA 0.05 mA 0.05 mA 0.05 mA
最大供电电压 (Vsup) 5.5 V 5.25 V 5.25 V 5.5 V 5.5 V 5.5 V
最小供电电压 (Vsup) 4.5 V 4.75 V 4.75 V 4.5 V 4.5 V 4.5 V
标称供电电压 (Vsup) 5 V 5 V 5 V 5 V 5 V 5 V
表面贴装 NO YES YES YES NO NO
技术 CMOS CMOS CMOS CMOS CMOS CMOS
温度等级 INDUSTRIAL INDUSTRIAL COMMERCIAL COMMERCIAL COMMERCIAL COMMERCIAL
端子面层 Tin/Lead (Sn/Pb) Tin/Lead (Sn/Pb) Tin/Lead (Sn/Pb) Tin/Lead (Sn/Pb) Tin/Lead (Sn/Pb) Tin/Lead (Sn/Pb)
端子形式 THROUGH-HOLE J BEND J BEND J BEND THROUGH-HOLE THROUGH-HOLE
端子节距 2.54 mm 1.27 mm 1.27 mm 1.27 mm 2.54 mm 2.54 mm
端子位置 DUAL QUAD QUAD QUAD DUAL DUAL
处于峰值回流温度下的最长时间 NOT SPECIFIED NOT SPECIFIED NOT SPECIFIED NOT SPECIFIED NOT SPECIFIED NOT SPECIFIED
厂商名称 AMD(超微) - AMD(超微) - AMD(超微) AMD(超微)
Base Number Matches - 1 1 1 - 1
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A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF AG AH AI AJ AK AL AM AN AO AP AQ AR AS AT AU AV AW AX AY AZ B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF BG BH BI BJ BK BL BM BN BO BP BQ BR BS BT BU BV BW BX BY BZ C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF CG CH CI CJ CK CL CM CN CO CP CQ CR CS CT CU CV CW CX CY CZ D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF DG DH DI DJ DK DL DM DN DO DP DQ DR DS DT DU DV DW DX DZ
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