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PRELIMINARY

Am29DL16xC

16 Megabit (2 M x 8-Bit/1 M x 16-Bit)

CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory

DISTINCTIVE CHARACTERISTICS

ARCHITECTURAL ADVANTAGES

Simultaneous Read/Write operations

— Data can be continuously read from one bank while

executing erase/program functions in other bank

— Zero latency between read and write operations

Multiple bank architectures

— Three devices available with different bank sizes (refer

to Table 2)

Secured Silicon (SecSi) Sector: Extra 64 KByte sector

—

Factory locked and identifiable:

16 bytes available for

secure, random factory Electronic Serial Number;

verifiable as factory locked through autoselect

function. ExpressFlash option allows entire sector to

be available for factory-secured data

—

Customer lockable:

Can be read, programmed, or

erased just like other sectors. Once locked, data

cannot be changed

Zero Power Operation

— Sophisticated power management circuits reduce

power consumed during inactive periods to nearly

zero

Package options

— 48-ball FBGA

— 56-pin SSOP

— 48-pin TSOP

Top or bottom boot block

Manufactured on 0.32 µm process technology

Compatible with JEDEC standards

— Pinout and software compatible with

single-power-supply flash standard

PERFORMANCE CHARACTERISTICS

High performance

— Access time as fast 70 ns

— Program time: 7 µs/word typical utilizing Accelerate function

Ultra low power consumption (typical values)

— 2 mA active read current at 1 MHz

— 10 mA active read current at 5 MHz

— 200 nA in standby or automatic sleep mode

Minimum 1 million write cycles guaranteed per sector

20 Year data retention at 125°C

— Reliable operation for the life of the system

SOFTWARE FEATURES

Data Management Software (DMS)

— AMD-supplied software manages data programming

and erasing, enabling EEPROM emulation

— Eases sector erase limitations

Supports Common Flash Memory Interface (CFI)

Erase Suspend/Erase Resume

— Suspends erase operations to allow programming in

same bank

Data# Polling and Toggle Bits

— Provides a software method of detecting the status of

program or erase cycles

Unlock Bypass Program command

— Reduces overall programming time when issuing

multiple program command sequences

HARDWARE FEATURES

Any combination of sectors can be erased

Ready/Busy# output (RY/BY#)

— Hardware method for detecting program or erase

cycle completion

Hardware reset pin (RESET#)

— Hardware method of resetting the internal state

machine to reading array data

WP#/ACC input pin

— Write protect (WP#) function allows protection of two

outermost boot sectors, regardless of sector protect status

— Acceleration (ACC) function accelerates program

timing

Sector protection

— Hardware method of locking a sector, either

in-system or using programming equipment, to

prevent any program or erase operation within that

sector

— Temporary Sector Unprotect allows changing data in

protected sectors in-system

This document contains information on a product under development at Advanced Micro Devices. The information

is intended to help you evaluate this product. AMD reserves the right to change or discontinue work on this proposed

product without notice.

Publication#

21533

Rev:

Amendment/+5

Issue Date:

October 18, 1999

Refer to AMD’s Website (www.amd.com) for the latest information.

P R E L I M I N A R Y

GENERAL DESCRIPTION

The Am29DL16xC family consists of 16 megabit, 3.0

volt-only flash memory devices, organized as 1,048,576

words of 16 bits each or 2,097,152 bytes of 8 bits each.

Word mode data appears on DQ0–DQ15; byte mode

data appears on DQ0–DQ7. The device is designed to

be programmed in-system with the standard 3.0 volt

supply, and can also be programmed in standard

EPROM programmers.

The device is available with an access time of 70, 80,

90, or 120 ns. The devices are offered in 56-pin SSOP,

48-pin TSOP, and 48-ball FBGA packages. Standard

control pins—chip enable (CE#), write enable (WE#),

and output enable (OE#)—control normal read and

write operations, and avoid bus contention issues.

The device requires only a

single 3.0 volt power sup-

ply

for both read and write functions. Internally

generated and regulated voltages are provided for the

program and erase operations.

other flash sector, or may permanently lock their own

code there.

DMS (Data Management Software)

allows systems

to easily take advantage of the advanced architecture

of the simultaneous read/write product line by allowing

removal of EEPROM devices. DMS will also allow the

system software to be simplified, as it will perform all

functions necessary to modify data in file structures,

as opposed to single-byte modifications. To write or

update a particular piece of data (a phone number or

configuration data, for example), the user only needs

to state which piece of data is to be updated, and

where the updated data is located in the system. This

i s a n a d va n t a g e c o m p a r e d t o s y s te m s w h e r e

user-written software must keep track of the old data

location, status, logical to physical translation of the

data onto the Flash memory device (or memory de-

vices), and more. Using DMS, user-written software

does not need to interface with the Flash memory di-

rectly. Instead, the user's software accesses the Flash

memory by calling one of only six functions. AMD pro-

vides this software to simplify system design and

software integration efforts.

The device offers complete compatibility with the

JEDEC single-power-supply Flash command set

standard.

Commands are written to the command

Reading data out of the device is similar to reading

from other Flash or EPROM devices.

The host system can detect whether a program or

erase operation is complete by using the device

sta-

tus bits:

RY/BY# pin, DQ7 (Data# Polling) and

DQ6/DQ2 (toggle bits). After a program or erase cycle

has been completed, the device automatically returns

to reading array data.

The

sector erase architecture

allows memory sec-

tors to be erased and reprogrammed without affecting

the data contents of other sectors. The device is fully

erased when shipped from the factory.

Hardware data protection

measures include a low

detector that automatically inhibits write opera-

tions during power transitions. The

hardware sector

protection

feature disables both program and erase

operations in any combination of the sectors of mem-

o r y. T h i s c a n b e a c h i ev e d i n - s y s t e m o r v i a

programming equipment.

The device offers two power-saving features. When

addresses have been stable for a specified amount of

time, the device enters the

automatic sleep mode.

The system can also place the device into the

standby mode.

Power consumption is greatly re-

duced in both modes.

Simultaneous Read/Write Operations with

Zero Latency

The Simultaneous Read/Write architecture provides

simultaneous operation

by dividing the memory

space into two banks. The device can improve overall

system performance by allowing a host system to pro-

gram or erase in one bank, then immediately and

simultaneously read from the other bank, with zero la-

tency. This releases the system from waiting for the

completion of program or erase operations.

The Am29DL16xC device family uses multiple bank

architectures to provide flexibility for different applica-

tions. Three devices are available with the following

bank sizes:

Device

DL162

DL163

DL164

Bank 1

2 Mb

4 Mb

8 Mb

Bank 2

14 Mb

12 Mb

8 Mb

Am29DL16xC Features

The

Secured Silicon (SecSi) Sector

is an extra 64

Kbit sector capable of being permanently locked by

AMD or customers. The

SecSi Sector Indicator Bit

(DQ7) is permanently set to a 1 if the part is

factory

locked,

and set to a 0 if

customer lockable.

This way,

customer lockable parts can never be used to replace

a factory locked part.

Factory locked parts provide several options. The

SecSi Sector may store a secure, random 16 byte

ESN (Electronic Serial Number), customer code (pro-

grammed through AMD’s ExpressFlash service), or

both. Customer Lockable parts may utilize the SecSi

Sector as bonus space, reading and writing like any

Am29DL16xC

P R E L I M I N A R Y

PRODUCT SELECTOR GUIDE

Part Number

Speed Option

Max Access Time (ns)

CE# Access (ns)

OE# Access (ns)

Standard Voltage Range: V

= 2.7–3.6 V

70, 70R

Am29DL16xC

120

BLOCK DIAGRAM

OE# BYTE#

Y-Decoder

A0–A19

Upper Bank Address

Upper Bank

Latches and Control Logic

RY/BY#

A0–A19

RESET#

WE#

CE#

BYTE#

WP#/ACC

DQ0–DQ15

STATE

CONTROL

COMMAND

X-Decoder

Status

DQ0–DQ15

Control

A0–A19

X-Decoder

Lower Bank

A0–A19

Lower Bank Address

Latches and

Control Logic

Y-Decoder

DQ0–DQ15

A0–A19

21533C-1

Am29DL16xC

P R E L I M I N A R Y

CONNECTION DIAGRAMS

A15

A14

A13

A12

A11

A10

A19

WE#

RESET#

WP#/ACC

RY/BY#

A18

A17

48-Pin Standard TSOP

A16

BYTE#

DQ15/A-1

DQ7

DQ14

DQ6

DQ13

DQ5

DQ12

DQ4

DQ11

DQ3

DQ10

DQ2

DQ9

DQ1

DQ8

DQ0

OE#

CE#

21533C-2

WP#/ACC

RY/BY#

A18

A17

CE#

OE#

DQ0

DQ8

DQ1

DQ9

DQ2

DQ10

DQ3

DQ11

56-Pin SSOP

RESET#

WE#

A19

A10

A11

A12

A13

A14

A15

A16

BTYE#

DQ15/A-1

DQ7

DQ14

DQ6

DQ13

DQ5

DQ12

DQ4

Am29DL16xC

P R E L I M I N A R Y

CONNECTION DIAGRAMS

48-Ball FBGA

Top View, Balls Facing Down

A13

WE#

A12

RESET#

A14

A10

A18

A15

A11

A19

A16

DQ7

DQ5

DQ2

DQ0

DQ6

DQ4

DQ3

DQ1

BYTE# DQ15/A-1

DQ14

DQ12

DQ10

DQ8

CE#

DQ13

DQ11

DQ9

OE#

RY/BY# WP#/ACC

A17

21533C-4

Special Handling Instructions for FBGA

Package

Special handling is required for Flash Memory prod-

ucts in FBGA packages.

Flash memory devices in FBGA packages may be

damaged if exposed to ultrasonic cleaning methods.

The package and/or data integrity may be compro-

mised if the package body is exposed to temperatures

above 150°C for prolonged periods of time.

Am29DL16xC