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Am29DL16xC

Data Sheet

RETIRED

PRODUCT

This product has been retired and is not recommended for designs. For new designs that do not

require simultaneous read/write (SRW) operations, the S29AL016D supersedes Am29DL16xC. For

new designs that require SRW, the S29JL032H supersedes Am29DL16xC. Please refer to the

Am29AL16xD and S29JL032H data sheets for specifications and ordering information. Availability

of this document is retained for reference and historical purposes only.

The following document contains information on Spansion memory products.

Continuity of Specifications

There is no change to this data sheet as a result of offering the device as a Spansion product. Any

changes that have been made are the result of normal data sheet improvement and are noted in the

document revision summary.

For More Information

Please contact your local sales office for additional information about Spansion memory solutions.

Publication Number

21533

Revision

Amendment

Issue Date

September 7, 2007

THIS PAGE LEFT INTENTIONALLY BLANK.

DATA SHEET

Am29DL16xC

16 Megabit (2 M x 8-Bit/1 M x 16-Bit)

CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory

This product has been retired and is not recommended for designs. For new designs that do not require simultaneous read/write (SRW) operations, the S29AL016D supersedes

Am29DL16xC. For new designs that require SRW, the S29JL032H supersedes Am29DL16xC. Please refer to the Am29AL16xD and S29JL032H data sheets for specifications and ordering

information. Availability of this document is retained for reference and historical purposes only.

DISTINCTIVE CHARACTERISTICS

ARCHITECTURAL ADVANTAGES

■

Simultaneous Read/Write operations

— Data can be continuously read from one bank while

executing erase/program functions in other bank

— Zero latency between read and write operations

■

Multiple bank architectures

— Two devices available with different bank sizes (refer

to Table 3)

■

Secured Silicon (SecSi) Sector: Extra 64 KByte

sector

—

Factory locked and identifiable:

16 bytes available for

secure, random factory Electronic Serial Number;

verifiable as factory locked through autoselect

function. ExpressFlash option allows entire sector to

be available for factory-secured data

—

Customer lockable:

Can be read, programmed, or

erased just like other sectors. Once locked, data

cannot be changed

■

Zero Power Operation

— Sophisticated power management circuits reduce

power consumed during inactive periods to nearly

zero

■

Package options

— 48-ball FBGA

— 56-pin SSOP

— 48-pin TSOP

■

Top or bottom boot block

■

Manufactured on 0.32 µm process technology

■

Compatible with JEDEC standards

— Pinout and software compatible with

single-power-supply flash standard

PERFORMANCE CHARACTERISTICS

■

High performance

— Access time as fast 70 ns

— Program time: 7 µs/word typical utilizing Accelerate

function

■

Ultra low power consumption (typical values)

— 2 mA active read current at 1 MHz

— 10 mA active read current at 5 MHz

— 200 nA in standby or automatic sleep mode

■

Minimum 1 million write cycles guaranteed per sector

■

20 Year data retention at 125°C

— Reliable operation for the life of the system

SOFTWARE FEATURES

■

Data Management Software (DMS)

— AMD-supplied software manages data programming

and erasing, enabling EEPROM emulation

— Eases sector erase limitations

■

Supports Common Flash Memory Interface (CFI)

■

Erase Suspend/Erase Resume

— Suspends erase operations to allow programming in

same bank

■

Data# Polling and Toggle Bits

— Provides a software method of detecting the status of

program or erase cycles

■

Unlock Bypass Program command

— Reduces overall programming time when issuing

multiple program command sequences

HARDWARE FEATURES

■

Any combination of sectors can be erased

■

Ready/Busy# output (RY/BY#)

— Hardware method for detecting program or erase

cycle completion

■

Hardware reset pin (RESET#)

— Hardware method of resetting the internal state

machine to reading array data

■

WP#/ACC input pin

— Write protect (WP#) function allows protection of two

outermost boot sectors, regardless of sector protect

status

— Acceleration (ACC) function provides accelerated

program times

■

Sector protection

— Hardware method of locking a sector, either

in-system or using programming equipment, to

prevent any program or erase operation within that

sector

— Temporary Sector Unprotect allows changing data in

protected sectors in-system

This Data Sheet states AMD’s current technical specifications regarding the Product described herein. This Data

Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.

Publication#

21533

Revision:

Amendment:

Issue Date:

September 7, 2007

D A T A

S H E E T

GENERAL DESCRIPTION

The Am29DL16xC family consists of 16 megabit, 3.0

volt-only flash memor y devices, organized as

1,048,576 words of 16 bits each or 2,097,152 bytes of

8 bits each. Word mode data appears on DQ0–DQ15;

byte mode data appears on DQ0–DQ7. The device is

designed to be programmed in-system with the stan-

dard 3.0 volt V

supply, and can also be programmed

in standard EPROM programmers.

The device is available with an access time of 70, 90,

or 120 ns. The devices are offered in 56-pin SSOP,

48-pin TSOP, and 48-ball FBGA packages. Standard

control pins—chip enable (CE#), write enable (WE#),

and output enable (OE#)—control normal read and

write operations, and avoid bus contention issues.

The device requires only a

single 3.0 volt power sup-

ply

for both read and write functions. Internally gener-

ated and regulated voltages are provided for the

program and erase operations.

other flash sector, or may permanently lock their own

code there.

DMS (Data Management Software)

allows systems

to easily take advantage of the advanced architecture

of the simultaneous read/write product line by allowing

removal of EEPROM devices. DMS will also allow the

system software to be simplified, as it will perform all

functions necessary to modify data in file structures,

as opposed to single-byte modifications. To write or

update a particular piece of data (a phone number or

configuration data, for example), the user only needs

to state which piece of data is to be updated, and

where the updated data is located in the system. This

i s a n a d va n t a g e c o m p a r e d t o s y s t e m s w h e r e

user-written software must keep track of the old data

location, status, logical to physical translation of the

data onto the Flash memory device (or memory de-

vices), and more. Using DMS, user-written software

does not need to interface with the Flash memory di-

rectly. Instead, the user's software accesses the Flash

memory by calling one of only six functions. AMD pro-

vides this software to simplify system design and soft-

ware integration efforts.

The device offers complete compatibility with the

JEDEC single-power-supply Flash command set

standard.

Commands are written to the command

Reading data out of the device is similar to reading

from other Flash or EPROM devices.

The host system can detect whether a program or

erase operation is complete by using the device

sta-

tus bits:

RY/BY# pin, DQ7 (Data# Polling) and

DQ6/DQ2 (toggle bits). After a program or erase cycle

has been completed, the device automatically returns

to reading array data.

The

sector erase architecture

allows memory sec-

tors to be erased and reprogrammed without affecting

the data contents of other sectors. The device is fully

erased when shipped from the factory.

Hardware data protection

measures include a low

detector that automatically inhibits write opera-

tions during power transitions. The

hardware sector

protection

feature disables both program and erase

operations in any combination of the sectors of mem-

ory. This can be achieved in-system or via program-

ming equipment.

The device offers two power-saving features. When

addresses have been stable for a specified amount of

time, the device enters the

automatic sleep mode.

The system can also place the device into the

standby mode.

Power consumption is greatly re-

duced in both modes.

Simultaneous Read/Write Operations with

Zero Latency

The Simultaneous Read/Write architecture provides

simultaneous operation

by dividing the memory

space into two banks. The device can improve overall

system performance by allowing a host system to pro-

gram or erase in one bank, then immediately and si-

multaneously read from the other bank, with zero

latency. This releases the system from waiting for the

completion of program or erase operations.

The Am29DL16xC device family uses multiple bank

architectures to provide flexibility for different applica-

tions. Two devices are available with the following

bank sizes:

Device

DL162

DL163

Bank 1

Bank 2

Am29DL16xC Features

The

Secured Silicon (SecSi) Sector

is an extra 64

Kbit sector capable of being permanently locked by

AMD or customers. The

SecSi Sector Indicator Bit

(DQ7) is permanently set to a 1 if the part is

factory

locked,

and set to a 0 if

customer lockable.

This way,

customer lockable parts can never be used to replace

a factory locked part.

Factory locked parts provide several options. The

SecSi Sector may store a secure, random 16 byte

ESN (Electronic Serial Number), customer code (pro-

grammed through AMD’s ExpressFlash service), or

both. Customer Lockable parts may utilize the SecSi

Sector as bonus space, reading and writing like any

Am29DL16xC

September 7, 2007 21533C2

D A T A

S H E E T

TABLE OF CONTENTS

Distinctive Characteristics . . . . . . . . . . . . . . . . . . 1

General Description . . . . . . . . . . . . . . . . . . . . . . . . 2

Simultaneous Read/Write Operations with Zero Latency ......... 2

Am29DL16xC Features ............................................................ 2

Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 4

Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . . 5

Special Handling Instructions for FBGA Package ..................... 6

Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 8

Device Bus Operations . . . . . . . . . . . . . . . . . . . . . 10

Table 1. Am29DL16xC Device Bus Operations ..............................10

DQ6: Toggle Bit I .................................................................... 29

Figure 6. Toggle Bit Algorithm........................................................ 29

DQ2: Toggle Bit II ................................................................... 30

Reading Toggle Bits DQ6/DQ2 ............................................... 30

DQ5: Exceeded Timing Limits ................................................ 30

DQ3: Sector Erase Timer ....................................................... 30

Table 15. Write Operation Status ................................................... 31

Absolute Maximum Ratings . . . . . . . . . . . . . . . . 32

Figure 7. Maximum Negative Overshoot Waveform ...................... 32

Figure 8. Maximum Positive Overshoot Waveform........................ 32

DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 33

Figure 9. I

CC1

Current vs. Time (Showing Active and

Automatic Sleep Currents) ............................................................. 34

Figure 10. Typical I

CC1

vs. Frequency ............................................ 34

Requirements for Reading Array Data ................................... 10

Writing Commands/Command Sequences ............................ 11

Simultaneous Read/Write Operations with Zero Latency ....... 11

Automatic Sleep Mode ........................................................... 11

RESET#: Hardware Reset Pin ............................................... 12

Output Disable Mode .............................................................. 12

Table 2. Am29DL16xC Device Bank Divisions ...............................12

Table 3. Sector Addresses for Top Boot Sector Devices ................13

SecSi Sector Addresses for Top Boot Devices.............................. 13

Table 5. Sector Addresses for Bottom Boot Sector Devices ...........14

SecSi Sector Addresses for Bottom Boot Devices......................... 14

Table 7. Am29DL16xC Autoselect Codes, (High Voltage Method) 15

Table 8. Top Boot Sector/Sector Block Addresses for

Protection/Unprotection ...................................................................16

Table 9. Bottom Boot Sector/Sector Block Addresses for Protec-

tion/Unprotection .............................................................................16

Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Figure 11. Test Setup.................................................................... 35

Figure 12. Input Waveforms and Measurement Levels ................. 35

AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 36

Figure 13. Read Operation Timings ............................................... 36

Figure 14. Reset Timings ............................................................... 37

Word/Byte Configuration (BYTE#) .......................................... 38

Figure 15. BYTE# Timings for Read Operations............................ 38

Figure 16. BYTE# Timings for Write Operations............................ 38

Erase and Program Operations .............................................. 39

Figure 17. Program Operation Timings..........................................

Figure 18. Accelerated Program Timing Diagram..........................

Figure 19. Chip/Sector Erase Operation Timings ..........................

Figure 20. Back-to-back Read/Write Cycle Timings ......................

Figure 21. Data# Polling Timings (During Embedded Algorithms).

Figure 22. Toggle Bit Timings (During Embedded Algorithms)......

Figure 23. DQ2 vs. DQ6.................................................................

Write Protect (WP#) ................................................................ 17

Temporary Sector/Sector Block Unprotect ............................. 17

Figure 1. Temporary Sector Unprotect Operation........................... 17

Figure 2. In-System Sector/Sector Block Protect and

Unprotect Algorithms....................................................................... 18

Temporary Sector/Sector Block Unprotect ............................. 44

Figure 24. Temporary Sector/Sector Block Unprotect

Timing Diagram.............................................................................. 44

Figure 25. Sector/Sector Block Protect and Unprotect

Timing Diagram.............................................................................. 45

SecSi (Secured Silicon) Sector Flash Memory Region .......... 19

Hardware Data Protection ...................................................... 19

Common Flash Memory Interface (CFI) . . . . . . . 20

Table 10. CFI Query Identification String ........................................ 20

System Interface String................................................................... 21

Table 12. Device Geometry Definition ............................................ 21

Table 13. Primary Vendor-Specific Extended Query ...................... 22

Alternate CE# Controlled Erase and Program Operations ..... 46

Figure 26. Alternate CE# Controlled Write (Erase/Program)

Operation Timings.......................................................................... 47

Command Definitions . . . . . . . . . . . . . . . . . . . . . . 23

Reading Array Data ................................................................ 23

Reset Command ..................................................................... 23

Autoselect Command Sequence ............................................ 23

Enter SecSi Sector/Exit SecSi Sector Command Sequence .. 24

Byte/Word Program Command Sequence ............................. 24

Figure 3. Program Operation .......................................................... 25

Chip Erase Command Sequence ........................................... 25

Sector Erase Command Sequence ........................................ 25

Erase Suspend/Erase Resume Commands ........................... 26

Figure 4. Erase Operation............................................................... 26

Table 14. Am29DL16xC Command Definitions .............................. 27

Write Operation Status . . . . . . . . . . . . . . . . . . . . . 28

DQ7: Data# Polling ................................................................. 28

Figure 5. Data# Polling Algorithm ................................................... 28

Erase And Programming Performance . . . . . . . 48

Latchup Characteristics . . . . . . . . . . . . . . . . . . . . 48

TSOP And SO Pin Capacitance . . . . . . . . . . . . . . 48

Data Retention. . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 49

SSO056—56-Pin Shrink Small Outline Package (SSOP)

(measured in millimeters) ....................................................... 49

FBC048—48-Ball Fine-Pitch Ball Grid Array (FBGA)

8 x 9 mm (measured in millimeters) ........................................ 50

TS 048—48-Pin Standard TSOP (measured in millimeters) .. 51

Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 52

Revision B .............................................................................. 52

Revision B+1 .......................................................................... 52

Revision C .............................................................................. 52

Revision C1 (May 8, 2006) ..................................................... 52

Revision C2 (September 7, 2007) .......................................... 52

September 7, 2007 21533C2

Am29DL16xC

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