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Am29DL32xG

Data Sheet

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ADVANCE INFORMATION

Am29DL32xG

32 Megabit (4 M x 8-Bit/2 M x 16-Bit)

CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory

DISTINCTIVE CHARACTERISTICS

ARCHITECTURAL ADVANTAGES

■

Simultaneous Read/Write operations

— Data can be continuously read from one bank while

executing erase/program functions in other bank

— Zero latency between read and write operations

■

Multiple bank architectures

— Three devices available with different bank sizes

(refer to Table 3)

■

256-byte SecSi (Secured Silicon) Sector

—

Factory locked and identifiable:

16 bytes available for

secure, random factory Electronic Serial Number;

verifiable as factory locked through autoselect

function. ExpressFlash option allows entire sector to

be available for factory-secured data

—

Customer lockable:

One time programmable. Once

locked, data cannot be changed.

■

Zero Power Operation

— Sophisticated power management circuits reduce

power consumed during inactive periods to nearly

zero

■

Package options

— 63-ball FBGA

— 48-ball FBGA

— 48-pin TSOP

— 64-ball Fortified BGA

■

Top or bottom boot block

■

Manufactured on 0.17 µm process technology

■

Compatible with JEDEC standards

— Pinout and software compatible with

single-power-supply flash standard

PERFORMANCE CHARACTERISTICS

■

High performance

— Access time as fast 70 ns

— Program time: 4 µs/word typical utilizing Accelerate

function

■

Ultra low power consumption (typical values)

— 2 mA active read current at 1 MHz

— 10 mA active read current at 5 MHz

— 200 nA in standby or automatic sleep mode

■

Minimum 1 million erase cycles guaranteed per

sector

■

20 year data retention at 125°C

— Reliable operation for the life of the system

SOFTWARE FEATURES

■

Data Management Software (DMS)

— AMD-supplied software manages data programming,

enabling EEPROM emulation

— Eases historical sector erase flash limitations

■

Supports Common Flash Memory Interface (CFI)

■

Erase Suspend/Erase Resume

— Suspends erase operations to allow programming in

same bank

■

Data# Polling and Toggle Bits

— Provides a software method of detecting the status of

program or erase cycles

■

Unlock Bypass Program command

— Reduces overall programming time when issuing

multiple program command sequences

HARDWARE FEATURES

■

Any combination of sectors can be erased

■

Ready/Busy# output (RY/BY#)

— Hardware method for detecting program or erase

cycle completion

■

Hardware reset pin (RESET#)

— Hardware method of resetting the internal state

machine to the read mode

■

WP#/ACC input pin

— Write protect (WP#) function allows protection of two

outermost boot sectors, regardless of sector protect

status

— Acceleration (ACC) function accelerates program

timing

■

Sector protection

— Hardware method of locking a sector, either

in-system or using programming equipment, to

prevent any program or erase operation within that

sector

— Temporary Sector Unprotect allows changing data in

protected sectors in-system

This document contains information on a product under development at Advanced Micro Devices. The information

is intended to help you evaluate this product. AMD reserves the right to change or discontinue work on this proposed

product without notice.

Publication#

25686

Rev: B Amendment/3

Issue Date:

April 21, 2003

Refer to AMD’s Website (www.amd.com) for the latest information.

A D V A N C E

I N F O R M A T I O N

GENERAL DESCRIPTION

The Am29DL32xG family consists of 32 megabit, 3.0

volt-only flas h memory dev ices, or ganiz ed as

2,097,152 words of 16 bits each or 4,194,304 bytes of

8 bits each. Word mode data appears on DQ15–DQ0;

byte mode data appears on DQ7–DQ0. The device is

designed to be programmed in-system with the stan-

dard 3.0 volt V

supply, and can also be programmed

in standard EPROM programmers.

The devices are available with an access time of 70,

90, or 120 ns. The devices are offered in 48-pin TSOP,

48-ball or 63-ball FBGA, and 64-ball Fortified BGA

packages. Standard control pins—chip enable (CE#),

write enable (WE#), and output enable (OE#)—control

normal read and write operations, and avoid bus con-

tention issues.

The devices requires only a

single 3.0 volt power

supply

for both read and write functions. Internally

generated and regulated voltages are provided for the

program and erase operations.

grammed through AMD’s ExpressFlash service), or

both.

DMS (Data Management Software)

allows systems

to easily take advantage of the advanced architecture

of the simultaneous read/write product line by allowing

removal of EEPROM devices. DMS will also allow the

system software to be simplified, as it will perform all

functions necessary to modify data in file structures,

as opposed to single-byte modifications. To write or

update a particular piece of data (a phone number or

configuration data, for example), the user only needs

to state which piece of data is to be updated, and

where the updated data is located in the system. This

i s a n a dv a n ta ge c om pa r e d to s y s te ms wh e r e

user-written software must keep track of the old data

location, status, logical to physical translation of the

data onto the Flash memory device (or memory de-

vices), and more. Using DMS, user-written software

does not need to interface with the Flash memory di-

rectly. Instead, the user's software accesses the Flash

memory by calling one of only six functions. AMD pro-

vides this software to simplify system design and soft-

ware integration efforts.

The device offers complete compatibility with the

JEDEC single-power-supply Flash command set

standard.

Commands are written to the command

Reading data out of the device is similar to reading

from other Flash or EPROM devices.

The host system can detect whether a program or

erase operation is complete by using the device

sta-

tus bits:

RY/BY# pin, DQ7 (Data# Polling) and

DQ6/DQ2 (toggle bits). After a program or erase cycle

has been completed, the device automatically returns

to the read mode.

The

sector erase architecture

allows memory sec-

tors to be erased and reprogrammed without affecting

the data contents of other sectors. The device is fully

erased when shipped from the factory.

Hardware data protection

measures include a low

detector that automatically inhibits write opera-

tions during power transitions. The

hardware sector

protection

feature disables both program and erase

operations in any combination of the sectors of mem-

ory. This can be achieved in-system or via program-

ming equipment.

The device offers two power-saving features. When

addresses have been stable for a specified amount of

time, the device enters the

automatic sleep mode.

The system can also place the device into the

standby mode.

Power consumption is greatly re-

duced in both modes.

Simultaneous Read/Write Operations with

Zero Latency

The Simultaneous Read/Write architecture provides

simultaneous operation

by dividing the memory

space into two banks. The device can improve overall

system performance by allowing a host system to pro-

gram or erase in one bank, then immediately and si-

multaneously read from the other bank, with zero

latency. This releases the system from waiting for the

completion of program or erase operations.

The Am29DL32xG device family uses multiple bank

architectures to provide flexibility for different applica-

tions. Three devices are available with the following

bank sizes:

Device

DL322

DL323

DL324

Bank 1

Bank 2

Am29DL32xG Features

The

SecSi (Secured Silicon) Sector

is an extra sector

capable of being permanently locked by AMD or cus-

tomers. The

SecSi Indicator Bit

(DQ7) is perma-

nently set to a 1 if the part is

factory locked,

and set

to a 0 if

customer lockable.

This way, customer lock-

able parts can never be used to replace a factory

locked part.

Current version of device has 256

bytes, which differs from previous versions of this

device.

Factory locked parts provide several options. The

SecSi Sector may store a secure, random 16 byte

ESN (Electronic Serial Number), customer code (pro-

Am29DL32xG

April 21, 2003

A D V A N C E

I N F O R M A T I O N

TABLE OF CONTENTS

Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 4

Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . . 5

Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 8

Device Bus Operations . . . . . . . . . . . . . . . . . . . . . 10

Table 1. Device Bus Operations ...........................................................10

Figure 3. Program Operation ................................................................ 24

Chip Erase Command Sequence ................................................. 24

Sector Erase Command Sequence .............................................. 25

Erase Suspend/Erase Resume Commands ................................ 25

Figure 4. Erase Operation .................................................................... 26

Table 13. Command Definitions ........................................................... 27

Write Operation Status . . . . . . . . . . . . . . . . . . . . 28

DQ7: Data# Polling ...................................................................... 28

Figure 5. Data# Polling Algorithm ......................................................... 28

Word/Byte Configuration .............................................................. 10

Requirements for Reading Array Data ......................................... 10

Writing Commands/Command Sequences .................................. 11

Accelerated Program Operation ...................................................11

Autoselect Functions .................................................................... 11

Simultaneous Read/Write Operations

with Zero Latency ......................................................................... 11

Standby Mode .............................................................................. 11

Automatic Sleep Mode ................................................................. 11

RESET#: Hardware Reset Pin .....................................................12

Output Disable Mode ................................................................... 12

Table 2. Device Bank Divisions .............................................................12

Table 3. Top Boot Sector Addresses ...................................................13

Table 4. Top Boot SecSi

Sector Addresses ..................................... 14

Table 5. Bottom Boot SecSi

Sector Addresses ................................ 14

RY/BY#: Ready/Busy# ................................................................. 29

DQ6: Toggle Bit I .......................................................................... 29

Figure 6. Toggle Bit Algorithm .............................................................. 29

DQ2: Toggle Bit II ......................................................................... 30

Reading Toggle Bits DQ6/DQ2 .................................................... 30

DQ5: Exceeded Timing Limits ...................................................... 30

DQ3: Sector Erase Timer ............................................................. 30

Table 14. Write Operation Status ......................................................... 31

Absolute Maximum Ratings . . . . . . . . . . . . . . . . 32

Figure 7. Maximum Negative Overshoot Waveform ............................. 32

Figure 8. Maximum Positive Overshoot Waveform .............................. 32

DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 33

Figure 9. I

CC1

Current vs. Time (Showing Active and

Automatic Sleep Currents).................................................................... 34

Figure 10. Typical I

CC1

vs. Frequency................................................... 34

Autoselect Mode .......................................................................... 15

Table 6. Autoselect Codes, (High Voltage Method) .............................15

Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Figure 11. Test Setup .......................................................................... 35

Figure 12. Input Waveforms and Measurement Levels ........................ 35

Sector/Sector Block Protection and Unprotection ........................ 16

Table 7. Top Boot Sector/Sector Block Addresses

for Protection/Unprotection ...................................................................16

Table 8. Bottom Boot Sector/Sector Block Addresses

for Protection/Unprotection ...................................................................16

AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 36

Figure 13. Read Operation Timings...................................................... 36

Figure 14. Reset Timings...................................................................... 37

Write Protect (WP#) ..................................................................... 17

Temporary Sector Unprotect ........................................................ 17

Figure 1. Temporary Sector Unprotect Operation................................. 17

Figure 2. In-System Sector Protection/

Sector Unprotection Algorithms ............................................................ 18

Word/Byte Configuration (BYTE#) ............................................... 38

Figure 15. BYTE# Timings for Read Operations .................................. 38

Figure 16. BYTE# Timings for Write Operations .................................. 38

Erase and Program Operations ................................................... 39

Figure 17. Program Operation Timings ................................................

Figure 18. Accelerated Program Timing Diagram ................................

Figure 19. Chip/Sector Erase Operation Timings .................................

Figure 20. Back-to-back Read/Write Cycle Timings .............................

Figure 21. Data# Polling Timings (During Embedded Algorithms) .......

Figure 22. Toggle Bit Timings (During Embedded Algorithms) ............

Figure 23. DQ2 vs. DQ6 .......................................................................

SecSi

(Secured Silicon) Sector

Flash Memory Region .................................................................. 19

Factory Locked: SecSi Sector Programmed and Protected At the

Factory ......................................................................................... 19

Customer Lockable: SecSi Sector NOT Programmed or Protected At

the Factory ...................................................................................19

Hardware Data Protection ............................................................ 19

Low VCC Write Inhibit .................................................................. 20

Write Pulse “Glitch” Protection .....................................................20

Logical Inhibit ...............................................................................20

Power-Up Write Inhibit ................................................................. 20

Temporary Sector Unprotect ........................................................ 44

Figure 24. Temporary Sector Unprotect Timing Diagram ..................... 44

Figure 25. Sector/Sector Block Protect and Unprotect Timing Diagram 45

Alternate CE# Controlled Erase and Program Operations ........... 46

Figure 26. Alternate CE# Controlled Write (Erase/Program)

Operation Timings ................................................................................ 47

Common Flash Memory Interface (CFI) . . . . . . . 20

Table 9. CFI Query Identification String ................................................

Table 10. System Interface String.........................................................

Table 11. Device Geometry Definition ..................................................

Table 12. Primary Vendor-Specific Extended Query ............................

Command Definitions . . . . . . . . . . . . . . . . . . . . . . 22

Reading Array Data ...................................................................... 22

Reset Command .......................................................................... 23

Autoselect Command Sequence ..................................................23

Enter SecSi

Sector/Exit SecSi Sector

Command Sequence ................................................................... 23

Byte/Word Program Command Sequence ................................... 23

Unlock Bypass Command Sequence ........................................... 24

Erase And Programming Performance . . . . . . . 48

Latchup Characteristics . . . . . . . . . . . . . . . . . . . . 48

TSOP Pin and Fine-Pitch BGA Capacitance. . . . 48

Data Retention. . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 49

FBD063—63-ball Fine-Pitch Ball Grid Array (FBGA) 8 x 14 mm . 49

FBD048—Fine-Pitch Ball Grid Array, 6 x 12 mm ......................... 50

TS 048—Thin Small Outline Package .......................................... 51

Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 53

Revision A (November 7, 2001) ................................................... 53

April 21, 2003

Am29DL32xG

A D V A N C E

I N F O R M A T I O N

PRODUCT SELECTOR GUIDE

Part Number

Speed Rating

Standard Voltage Range: V

= 2.7–3.6 V

Am29DL32xG

120

Max Access Time (ns)

CE# Access (ns)

OE# Access (ns)

BLOCK DIAGRAM

OE# BYTE#

Y-Decoder

A20–A0

Upper Bank Address

Upper Bank

Latches and Control Logic

RY/BY#

A20–A0

RESET#

WE#

CE#

BYTE#

WP#/ACC

DQ15–DQ0

A20–A0

STATE

CONTROL

COMMAND

X-Decoder

Status

DQ15–DQ0

Control

DQ15–DQ0

X-Decoder

Lower Bank

A20–A0

Lower Bank Address

OE# BYTE#

Am29DL32xG

Latches and

Control Logic

Y-Decoder

DQ15–DQ0

A20–A0

April 21, 2003