PRELIMINARY
Am29DL322D/323D/324D
32 Megabit (4 M x 8-Bit/2 M x 16-Bit)
CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory
DISTINCTIVE CHARACTERISTICS
ARCHITECTURAL ADVANTAGES
s
Simultaneous Read/Write operations
— Data can be continuously read from one bank while
executing erase/program functions in other bank.
— Zero latency between read and write operations
s
Multiple bank architectures
— Three devices available with different bank sizes
(refer to Table 3)
s
SecSi™ (Secured Silicon) Sector: Extra 64 KByte
sector
—
Factory locked and identifiable:
16 bytes available for
secure, random factory Electronic Serial Number;
verifiable as factory locked through autoselect
function. ExpressFlash option allows entire sector to
be available for factory-secured data
—
Customer lockable:
Can be read, programmed, or
erased just like other sectors. Once locked, data
cannot be changed
s
Zero Power Operation
— Sophisticated power management circuits reduce
power consumed during inactive periods to nearly
zero.
s
Package options
— 63-ball FBGA
— 48-pin TSOP
s
Top or bottom boot block
s
Manufactured on 0.23 µm process technology
s
Compatible with JEDEC standards
— Pinout and software compatible with
single-power-supply flash standard
PERFORMANCE CHARACTERISTICS
s
High performance
— Access time as fast 70 ns
— Program time: 7 µs/word typical utilizing Accelerate
function
s
Ultra low power consumption (typical values)
— 2 mA active read current at 1 MHz
— 10 mA active read current at 5 MHz
— 200 nA in standby or automatic sleep mode
s
Minimum 1 million write cycles guaranteed per
sector
s
20 year data retention at 125°C
— Reliable operation for the life of the system
SOFTWARE FEATURES
s
Data Management Software (DMS)
— AMD-supplied software manages data programming,
enabling EEPROM emulation
— Eases historical sector erase flash limitations
s
Supports Common Flash Memory Interface (CFI)
s
Erase Suspend/Erase Resume
— Suspends erase operations to allow programming in
same bank
s
Data# Polling and Toggle Bits
— Provides a software method of detecting the status of
program or erase cycles
s
Unlock Bypass Program command
— Reduces overall programming time when issuing
multiple program command sequences
HARDWARE FEATURES
s
Any combination of sectors can be erased
s
Ready/Busy# output (RY/BY#)
— Hardware method for detecting program or erase
cycle completion
s
Hardware reset pin (RESET#)
— Hardware method of resetting the internal state
machine to the read mode
s
WP#/ACC input pin
— Write protect (WP#) function allows protection of two
outermost boot sectors, regardless of sector protect
status
— Acceleration (ACC) function accelerates program
timing
s
Sector protection
— Hardware method of locking a sector, either
in-system or using programming equipment, to
prevent any program or erase operation within that
sector
— Temporary Sector Unprotect allows changing data in
protected sectors in-system
This document contains information on a product under development at Advanced Micro Devices. The information
is intended to help you evaluate this product. AMD reserves the right to change or discontinue work on this proposed
product without notice.
Publication#
21534
Rev:
D
Amendment/+2
Issue Date:
August 3, 2000
Refer to AMD’s Website (www.amd.com) for the latest information.
P R E L I M I N A R Y
GENERAL DESCRIPTION
The Am29DL322D/323D/324D family consists of
32 megabit, 3.0 volt-only flash memory devices, orga-
nized as 2,097,152 words of 16 bits each or 4,194,304
bytes of 8 bits each. Word mode data appears on
DQ0–DQ15; byte mode data appears on DQ0–DQ7.
The device is designed to be programmed in-system
with the standard 3.0 volt V
CC
supply, and can also be
programmed in standard EPROM programmers.
The devices are available with an access time of 70,
90 or 120 ns. The devices are offered in 48-pin TSOP
and 63-ball FBGA packages. Standard control
pins—chip enable (CE#), write enable (WE#), and out-
put enable (OE#)—control normal read and write op-
erations, and avoid bus contention issues.
The devices requires only a
single 3.0 volt power
supply
for both read and write functions. Internally
generated and regulated voltages are provided for the
program and erase operations.
other flash sector, or may permanently lock their own
code there.
DMS (Data Management Software)
allows systems
to easily take advantage of the advanced architecture
of the simultaneous read/write product line by allowing
removal of EEPROM devices. DMS will also allow the
system software to be simplified, as it will perform all
functions necessary to modify data in file structures,
as opposed to single-byte modifications. To write or
update a particular piece of data (a phone number or
configuration data, for example), the user only needs
to state which piece of data is to be updated, and
where the updated data is located in the system. This
i s a n a d va n t a g e c o m p a r e d t o s y s te m s w h e r e
user-written software must keep track of the old data
location, status, logical to physical translation of the
data onto the Flash memory device (or memory de-
vices), and more. Using DMS, user-written software
does not need to interface with the Flash memory di-
rectly. Instead, the user's software accesses the Flash
memory by calling one of only six functions. AMD pro-
vides this software to simplify system design and soft-
ware integration efforts.
The device offers complete compatibility with the
JEDEC single-power-supply Flash command set
standard.
Commands are written to the command
register using standard microprocessor write timings.
Reading data out of the device is similar to reading
from other Flash or EPROM devices.
The host system can detect whether a program or
erase operation is complete by using the device
sta-
tus bits:
RY/BY# pin, DQ7 (Data# Polling) and
DQ6/DQ2 (toggle bits). After a program or erase cycle
has been completed, the device automatically returns
to the read mode.
The
sector erase architecture
allows memory sec-
tors to be erased and reprogrammed without affecting
the data contents of other sectors. The device is fully
erased when shipped from the factory.
Hardware data protection
measures include a low
V
CC
detector that automatically inhibits write opera-
tions during power transitions. The
hardware sector
protection
feature disables both program and erase
operations in any combination of the sectors of mem-
ory. This can be achieved in-system or via program-
ming equipment.
The device offers two power-saving features. When
addresses have been stable for a specified amount of
time, the device enters the
automatic sleep mode.
The system can also place the device into the
standby mode.
Power consumption is greatly re-
duced in both modes.
Simultaneous Read/Write Operations with
Zero Latency
The Simultaneous Read/Write architecture provides
simultaneous operation
by dividing the memory
space into two banks. The device can improve overall
system performance by allowing a host system to pro-
gram or erase in one bank, then immediately and si-
multaneously read from the other bank, with zero
latency. This releases the system from waiting for the
completion of program or erase operations.
The Am29DL32xD device family uses multiple bank
architectures to provide flexibility for different applica-
tions. Two devices are available with the following
bank sizes:
Device
DL322
DL323
DL324
Bank 1
4
8
16
Bank 2
28
24
16
Am29DL322D/323D/324D Features
The
SecSi™ (Secured Silicon) Sector
is an extra 64 Kbit
sector capable of being permanently locked by AMD
or customers. The
SecSi Indicator Bit
(DQ7) is per-
manently set to a 1 if the part is
factory locked,
and
set to a 0 if
customer lockable.
This way, customer
lockable parts can never be used to replace a factory
locked part.
Factory locked parts provide several options. The
SecSi Sector may store a secure, random 16 byte
ESN (Electronic Serial Number), customer code (pro-
grammed through AMD’s ExpressFlash service), or
both. Customer Lockable parts may utilize the SecSi
Sector as bonus space, reading and writing like any
2
Am29DL322D/323D/324D
August 3, 2000
P R E L I M I N A R Y
TABLE OF CONTENTS
Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 4
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . . 5
Special Handling Instructions for FBGA Package .......5
Figure 5. Data# Polling Algorithm .................................... 29
RY/BY#: Ready/Busy# .............................................. 30
DQ6: Toggle Bit I .......................................................30
Figure 6. Toggle Bit Algorithm ......................................... 30
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 8
Device Bus Operations . . . . . . . . . . . . . . . . . . . . . . 9
Table 1. Device Bus Operations .........................................9
DQ2: Toggle Bit II ......................................................31
Reading Toggle Bits DQ6/DQ2 .................................31
DQ5: Exceeded Timing Limits ...................................31
DQ3: Sector Erase Timer ..........................................31
Table 15. Write Operation Status .................................... 32
Word/Byte Configuration ............................................. 9
Requirements for Reading Array Data ........................9
Writing Commands/Command Sequences ...............10
Simultaneous Read/Write Operations
with Zero Latency ......................................................10
Standby Mode ........................................................... 10
Automatic Sleep Mode ..............................................10
RESET#: Hardware Reset Pin ..................................11
Output Disable Mode .................................................11
Table 2. Device Bank Divisions ........................................11
Table 3. Top Boot Sector Addresses ...............................12
Table 4. Top Boot SecSi™ Sector Addresses ................. 13
Table 5. Bottom Boot Sector Addresses ..........................14
Table 6. Bottom Boot SecSi™ Sector Addresses ............ 15
Absolute Maximum Ratings . . . . . . . . . . . . . . . . 33
Figure 7. Maximum Negative
Overshoot Waveform....................................................... 33
Figure 8. Maximum Positive
Overshoot Waveform....................................................... 33
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 9. I
CC1
Current vs. Time (Showing Active and
Automatic Sleep Currents)............................................... 35
Figure 10. Typical I
CC1
vs. Frequency.............................. 35
Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 11. Test Setup ..................................................... 36
Figure 12. Input Waveforms and Measurement Levels ... 36
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 37
Figure 13. Read Operation Timings................................. 37
Figure 14. Reset Timings................................................. 38
Autoselect Mode ........................................................ 16
Table 7. Autoselect Codes, (High Voltage Method) ........16
Word/Byte Configuration (BYTE#) ............................39
Figure 15. BYTE# Timings for Read Operations ............. 39
Figure 16. BYTE# Timings for Write Operations ............. 39
Sector/Sector Block Protection and Unprotection .....17
Table 8. Top Boot Sector/Sector Block Addresses
for Protection/Unprotection ...............................................17
Table 9. Bottom Boot Sector/Sector Block Addresses
for Protection/Unprotection ...............................................17
Erase and Program Operations ................................40
Figure 17. Program Operation Timings ...........................
Figure 18. Accelerated Program Timing Diagram ...........
Figure 19. Chip/Sector Erase Operation Timings ............
Figure 20. Back-to-back Read/Write Cycle Timings ........
Figure 21. Data# Polling Timings (During
Embedded Algorithms) ....................................................
Figure 22. Toggle Bit Timings (During
Embedded Algorithms) ....................................................
Figure 23. DQ2 vs. DQ6 ..................................................
41
41
42
43
43
44
44
Write Protect (WP#) ..................................................18
Temporary Sector Unprotect .....................................18
Figure 1. Temporary Sector Unprotect Operation ............ 18
Figure 2. In-System Sector Protection/
Sector Unprotection Algorithms........................................ 19
SecSi™ (Secured Silicon) Sector
Flash Memory Region ...............................................20
Hardware Data Protection .........................................20
Temporary Sector Unprotect .....................................45
Figure 24. Temporary Sector Unprotect Timing Diagram 45
Figure 25. Sector/Sector Block Protect and Unprotect
Timing Diagram ............................................................... 46
Common Flash Memory Interface (CFI) . . . . . . . 21
Table 10. CFI Query Identification String .........................
Table 11. System Interface String ....................................
Table 12. Device Geometry Definition..............................
Table 13. Primary Vendor-Specific Extended Query........
21
22
22
23
Alternate CE# Controlled Erase and
Program Operations ..................................................47
Figure 26. Alternate CE# Controlled Write (Erase/Program)
Operation Timings ........................................................... 48
Command Definitions . . . . . . . . . . . . . . . . . . . . . . 23
Reading Array Data ...................................................23
Reset Command .......................................................24
Autoselect Command Sequence ...............................24
Enter SecSi™ Sector/Exit SecSi Sector
Command Sequence .................................................24
Byte/Word Program Command Sequence ................24
Figure 3. Program Operation............................................ 25
Erase And Programming Performance . . . . . . .
Latchup Characteristics . . . . . . . . . . . . . . . . . . . .
TSOP And SO Pin Capacitance . . . . . . . . . . . . . .
Data Retention. . . . . . . . . . . . . . . . . . . . . . . . . . . .
49
49
49
49
FBD063—63-ball Fine-Pitch Ball Grid Array
(FBGA) 8 x 14 mm ....................................................50
TS 048—48-Pin Standard TSOP ..............................51
Chip Erase Command Sequence ..............................25
Sector Erase Command Sequence ...........................26
Erase Suspend/Erase Resume Commands ..............26
Figure 4. Erase Operation ................................................ 27
Table 14. Command Definitions ....................................... 28
Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 52
Revision D (December 17, 1999) ..............................53
Revision D+1 (June 21, 2000) ..................................53
Revision D+2 (August 3, 2000) .................................53
Write Operation Status . . . . . . . . . . . . . . . . . . . . . 29
DQ7: Data# Polling ....................................................29
August 3, 2000
Am29DL322D/323D/324D
3
P R E L I M I N A R Y
PRODUCT SELECTOR GUIDE
Part Number
Speed Option
Max Access Time (ns)
CE# Access (ns)
OE# Access (ns)
Standard Voltage Range: V
CC
= 2.7–3.6 V
Am29DL322D/323D/324D
70
70
70
30
90
90
90
40
120
120
120
50
BLOCK DIAGRAM
V
CC
V
SS
OE# BYTE#
Y-Decoder
A0–A20
Upper Bank Address
Upper Bank
Latches and Control Logic
RY/BY#
A0–A20
RESET#
WE#
CE#
BYTE#
WP#/ACC
DQ0–DQ15
A0–A20
STATE
CONTROL
&
COMMAND
REGISTER
X-Decoder
Status
DQ0–DQ15
Control
DQ0–DQ15
X-Decoder
Lower Bank
A0–A20
Lower Bank Address
4
Am29DL322D/323D/324D
Latches and
Control Logic
Y-Decoder
DQ0–DQ15
A0–A20
August 3, 2000
P R E L I M I N A R Y
CONNECTION DIAGRAMS
A15
A14
A13
A12
A11
A10
A9
A8
A19
A20
WE#
RESET#
NC
WP#/ACC
RY/BY#
A18
A17
A7
A6
A5
A4
A3
A2
A1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
A16
BYTE#
V
SS
DQ15/A-1
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
V
CC
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE#
V
SS
CE#
A0
48-Pin Standard TSOP
A8
NC
A7
NC
B8
NC
B7
NC
C7
A13
C6
A9
C5
WE#
C4
D7
A12
D6
A8
D5
RESET#
D4
63-Ball FBGA
Top View, Balls Facing Down
L8
NC*
M8
NC*
M7
NC*
E7
A14
E6
A10
E5
NC
E4
A18
E3
A6
E2
A2
F7
A15
F6
A11
F5
A19
F4
A20
F3
A5
F2
A1
G7
A16
G6
DQ7
G5
DQ5
G4
DQ2
G3
DQ0
G2
A0
H7
J7
K7
V
SS
K6
DQ6
K5
DQ4
K4
DQ3
K3
DQ1
K2
V
SS
L7
NC*
BYTE# DQ15/A-1
H6
DQ14
H5
DQ12
H4
DQ10
H3
DQ8
H2
CE#
J6
DQ13
J5
V
CC
J4
DQ11
J3
DQ9
J2
OE#
RY/BY# WP#/ACC
C3
A7
A2
NC*
A1
NC*
B1
C2
A3
D3
A17
D2
A4
L2
NC*
L1
M2
NC*
M1
NC*
* Balls are shorted together via the substrate but not connected to the die.
NC*
NC*
August 3, 2000
Am29DL322D/323D/324D
5
