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Am29DL400B

Data Sheet

RETIRED

PRODUCT

This product has been retired and is not recommended for designs. For new and current designs,

S29AL004D supersedes Am29DL400B and is the factory-recommended migration path. Please refer

to the S29AL004D datasheet for specifications and ordering information. Availability of this docu-

ment is retained for reference and historical purposes only.

April 2005

The following document specifies Spansion memory products that are now offered by both Advanced

Micro Devices and Fujitsu. Although the document is marked with the name of the company that

originally developed the specification, these products will be offered to customers of both AMD and

Fujitsu.

Continuity of Specifications

There is no change to this datasheet as a result of offering the device as a Spansion product. Any

changes that have been made are the result of normal datasheet improvement and are noted in the

document revision summary, where supported. Future routine revisions will occur when appro-

priate, and changes will be noted in a revision summary.

For More Information

Please contact your local AMD or Fujitsu sales office for additional information about Spansion

memory solutions.

Publication Number

21606

Revision

Amendment

Issue Date

June 7, 2005

THIS PAGE LEFT INTENTIONALLY BLANK.

Am29DL400B

4 Megabit (512 K x 8-Bit/256 K x 16-Bit)

CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory

This product has been retired and is not recommended for designs. For new and current designs, S29AL004D supersedes Am29DL400B and is the factory-recommended migration path.

Please refer to the S29AL004D datasheet for specifications and ordering information. Availability of this document is retained for reference and historical purposes only.

DISTINCTIVE CHARACTERISTICS

■

Simultaneous Read/Write operations

— Host system can program or erase in one bank,

then immediately and simultaneously read

from the other bank

— Zero latency between read and write

operations

— Read-while-erase

— Read-while-program

— Sectors can be locked in-system or via

programming equipment

— Temporary Sector Unprotect feature allows

code changes in previously locked sectors

■

Top or bottom boot block configurations

available

■

Embedded Algorithms

— Embedded Erase algorithm automatically

pre-programs and erases sectors or entire chip

— Embedded Program algorithm automatically

programs and verifies data at specified address

■

Single power supply operation

— 2.7 to 3.6 volt read and write operations for

battery-powered applications

■

Manufactured on 0.32 µm process

technology

■

High performance

— Access times as fast as 70 ns

■

Minimum 1 million program/erase cycles

guaranteed per sector

■

20-year data retention at 125° C

— Reliable operation for the life of the system

■

Low current consumption (typical

values at 5 MHz)

— 7 mA active read current

— 21 mA active read-while-program or read-

while-erase current

— 17 mA active program-while-erase-suspended

current

— 200 nA in standby mode

— 200 nA in automatic sleep mode

— Standard t

chip enable access time applies to

transition from automatic sleep mode to active

mode

■

Package options

— 44-pin SO

— 48-pin TSOP

■

Compatible with JEDEC standards

— Pinout and software compatible with

single-power-supply flash standard

— Superior inadvertent write protection

■

Data# Polling and Toggle Bits

— Provides a software method of detecting

program or erase cycle completion

■

Flexible sector architecture

— Two 16 Kword, two 8 Kword, four 4 Kword, and

six 32 Kword sectors in word mode

— Two 32 Kbyte, two 16 Kbyte, four 8 Kbyte, and

six 64 Kbyte sectors in byte mode

— Any combination of sectors can be erased

— Supports full chip erase

■

Ready/Busy# output (RY/BY#)

— Hardware method for detecting program or

erase cycle completion

■

Erase Suspend/Erase Resume

— Suspends or resumes erasing sectors to allow

reading and programming in other sectors

— No need to suspend if sector is in the other

bank

■

Unlock Bypass Program Command

— Reduces overall programming time when

issuing multiple program command sequences

■

Hardware reset pin (RESET#)

— Hardware method of resetting the device to

reading array data

■

Sector protection

— Hardware method of locking a sector to

prevent any program or erase operation within

that sector

This Data Sheet states AMD’s current technical specifications regarding the Products described herein. This Data Sheet may

be revised by subsequent versions or modifications due to changes in technical specifications.

Publication#

21606

Rev:

Amendment/+4

Issue Date:

June 7, 2005

GENERAL DESCRIPTION

The Am29DL400B is an 4 Mbit, 3.0 volt-only flash

memory device, organized as 262,144 words or

524,288 bytes. The device is offered in 44-pin SO

and 48-pin TSOP packages. The word-wide (x16)

data appears on DQ0–DQ15; the byte-wide (x8)

data appears on DQ0–DQ7. This device requires only

a single 3.0 volt V

supply to perform read, pro-

gram, and erase operations. A standard EPROM

programmer can also be used to program and erase

the device.

The standard device offers access times of 70, 80,

90, and 120 ns, allowing high-speed microprocessors

to operate without wait states. Standard control

pins—chip enable (CE#), write enable (WE#), and

output enable (OE#)—control read and write opera-

tions, and avoid bus contention issues.

The device requires only a

single 3.0 volt power

supply

for both read and write functions. Internally

generated and regulated voltages are provided for

the program and erase operations.

by requiring only two write cycles to program data

instead of four.

Device erasure occurs by executing the erase com-

mand sequence. This initiates the

Embedded Erase

algorithm—an internal algorithm that automatically

preprograms the array (if it is not already pro-

grammed) before executing the erase operation.

During erase, the device automatically times the

erase pulse widths and verifies proper cell margin.

The host system can detect whether a program or

erase operation is complete by observing the RY/BY#

pin, or by reading the DQ7 (Data# Polling) and DQ6

(toggle)

status bits.

After a program or erase cycle

has been completed, the device automatically re-

turns to reading array data.

The

sector erase architecture

allows memory sec-

tors to be erased and reprogrammed wi thout

affecting the data contents of other sectors. The de-

vice is fully erased when shipped from the factory.

Hardware data protection

measures include a low

detector that automatically inhibits write opera-

tions during power transitions. The

hardware

sector protection

feature disables both program

and erase operations in any combination of the sec-

tors of memory. This can be achieved in-system or

via programming equipment.

The

Erase Suspend

feature enables the user to put

erase on hold for any period of time to read data

from, or program data to, any sector within that

bank that is not selected for erasure. True back-

ground erase can thus be achieved. There is no need

to suspend the erase operation if the read data is in

the other bank.

The

hardware RESET# pin

terminates any opera-

tion in progress and resets the internal state

machine to reading array data. The RESET# pin may

be tied to the system reset circuitry. A system reset

would thus also reset the device to reading array

data, enabling the system microprocessor to read

the boot-up firmware from the Flash memory.

The device offers two power-saving features. When

addresses have been stable for a specified amount of

time, the device enters the

automatic sleep mode.

The system can also place the device into the

standby mode.

Power consumption is greatly re-

duced in both these modes.

AMD’s Flash technology combines years of Flash

memory manufacturing experience to produce the

hi ghe st l evels of qua lity, rel iabi lity, and cost

effectiveness. The device electrically erases all bits

within a sector simultaneously via Fowler-Nordheim

tunneling. The bytes are programmed one byte or

word at a time using hot electron injection.

Simultaneous Read/Write Operations with

Zero Latency

The Simultaneous Read/Write architecture provides

simultaneous operation

by dividing the memory

space into two banks. Bank 1 contains boot/parame-

ter sectors, and Bank 2 consists of larger, code

sectors of uniform size. The device can improve

overall system performance by allowing a host sys-

tem to program or erase in one bank, then

immediately and simultaneously read from the other

bank, with

zero latency.

This releases the system

from waiting for the completion of program or erase

operations.

Am29DL400B Features

The device offers complete compatibility with the

JEDEC single-power-supply Flash command set

standard.

Commands are written to the command

ings. Register contents serve as input to an internal

state machine that controls the erase and program-

ming circuitry. Write cycles also internally latch

addresses and data needed for the programming and

erase operations. Reading data out of the device is

similar to reading from other Flash or EPROM

devices.

Device programming occurs by executing the pro-

g ra m c o m m a n d s e q u e n c e . T h i s i n i t i a t e s t h e

Embedded Program

algorithm—an internal algo-

rithm that automatically times the program pulse

widths and verifies proper cell margin. The

Unlock

Bypass

mode facilitates faster programming times

Am29DL400B

TABLE OF CONTENTS

Product Selector Guide ..........................................

Block Diagram.........................................................

Connection Diagrams .............................................

Connection diagramS .............................................

Pin Description........................................................

Logic Symbol ..........................................................

Ordering Information ..............................................

Device Bus Operations...........................................

RY/BY#: Ready/Busy# ............................................................ 21

DQ6: Toggle Bit I .................................................................... 22

DQ2: Toggle Bit II ................................................................... 22

Reading Toggle Bits DQ6/DQ2 ............................................... 22

Figure 6. Toggle Bit Algorithm........................................................ 23

DQ5: Exceeded Timing Limits ................................................ 23

DQ3: Sector Erase Timer ....................................................... 23

Table 6. Write Operation Status ..................................................... 24

Table 1. Am29DL400B Device Bus Operations ................................9

Absolute Maximum Ratings................................. 25

Figure 7. Maximum Negative Overshoot Waveform ..................... 25

Figure 8. Maximum Positive Overshoot Waveform....................... 25

Word/Byte Configuration .......................................................... 9

Requirements for Reading Array Data ..................................... 9

Writing Commands/Command Sequences .............................. 9

Simultaneous Read/Write Operations with Zero

Latency ................................................................................... 10

Standby Mode ........................................................................ 10

Automatic Sleep Mode ........................................................... 10

RESET#: Hardware Reset Pin ............................................... 10

Output Disable Mode .............................................................. 11

Table 2. Am29DL400BT Top Boot Sector

Architecture .....................................................................................11

Table 3. Am29DL400BB Bottom Boot Sector

Architecture .....................................................................................12

Operating Ranges ................................................. 26

DC Characteristics................................................ 27

CMOS Compatible .................................................................. 27

Figure 9. I

CC1

Current vs. Time (Showing Active

and Automatic Sleep Currents) ...................................................... 28

Figure 10. Typical I

CC1

vs. Frequency ........................................... 28

Test Conditions..................................................... 29

Figure 11. Test Setup.................................................................... 29

Table 7. Test Specifications ........................................................... 29

Key to Switching Waveforms .................................................. 29

Figure 12. Input Waveforms and Measurement

Levels............................................................................................. 29

Autoselect Mode ..................................................................... 12

Table 4. Am29DL400B Autoselect Codes (High Voltage Method) ..13

Sector Protection/Unprotection ............................................... 13

Temporary Sector Unprotect .................................................. 13

Figure 1. Temporary Sector Unprotect Operation........................... 13

Figure 2. In-System Sector Protect/Unprotect

Algorithms ....................................................................................... 14

AC Characteristics................................................ 30

Read-Only Operations ........................................................... 30

Figure 13. Read Operation Timings ...............................................

Figure 14. Reset Timings ...............................................................

Figure 15. BYTE# Timings for Read Operations............................

Figure 16. BYTE# Timings for Write Operations............................

Figure 17. Program Operation Timings..........................................

Figure 18. Chip/Sector Erase Operation Timings ..........................

Figure 19. Back-to-Back Read/Write Cycle Timings ......................

Figure 20. Data# Polling Timings (During Embedded Algorithms).

Figure 21. Toggle Bit Timings (During Embedded Algorithms)......

Figure 22. DQ2 vs. DQ6.................................................................

Figure 23. Temporary Sector Unprotect Timing

Diagram..........................................................................................

Figure 24. Sector Protect/Unprotect Timing

Diagram..........................................................................................

Hardware Data Protection ...................................................... 15

Low VCC Write Inhibit ............................................................ 15

Write Pulse “Glitch” Protection ............................................... 15

Logical Inhibit .......................................................................... 15

Power-Up Write Inhibit ............................................................ 15

Command Definitions ........................................... 15

Reading Array Data ................................................................ 15

Reset Command ..................................................................... 15

Autoselect Command Sequence ............................................ 15

Byte/Word Program Command Sequence ............................. 16

Unlock Bypass Command Sequence ..................................... 16

Figure 3. Program Operation .......................................................... 17

Alternate CE# Controlled Erase/Program

Operations .............................................................................. 39

Figure 25. Alternate CE# Controlled Erase/Program

Operation Timings.......................................................................... 40

Chip Erase Command Sequence ........................................... 17

Sector Erase Command Sequence ........................................ 17

Erase Suspend/Erase Resume Commands ........................... 18

Figure 4. Erase Operation............................................................... 19

Command Definitions ........................................... 20

Table 5. Am29DL400B Command Definitions ................................20

Write Operation Status ......................................... 21

DQ7: Data# Polling ................................................................. 21

Figure 5. Data# Polling Algorithm ................................................... 21

Erase and Programming Performance ............... 41

Latchup Characteristics ....................................... 42

TSOP and SO Pin Capacitance............................ 42

Data Retention....................................................... 42

Physical Dimensions*........................................... 43

TS 048—48-Pin Standard TSOP ............................................ 43

TSR048—48-Pin Reverse TSOP ........................................... 44

SO 044—44-Pin Small Outline ............................................... 45

Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 46

Am29DL400B