FINAL
Am29F040
4 Megabit (524,288 x 8-Bit) CMOS 5.0 Volt-only,
Sector Erase Flash Memory
DISTINCTIVE CHARACTERISTICS
s
5.0 V
±
10% for read and write operations
— Minimizes system level power requirements
s
Compatible with JEDEC-standards
— Pinout and software compatible with single-
power-supply Flash
— Superior inadvertent write protection
s
Package options
— 32-pin PLCC
— 32-pin TSOP
— 32-pin PDIP
s
Minimum 100,000 write/erase cycles guaranteed
s
High performance
— 55 ns maximum access time
s
Sector erase architecture
— Uniform sectors of 64 Kbytes each
— Any combination of sectors can be erased.
Also supports full chip erase.
s
Sector protection
— Hardware method that disables any combination
of sectors from write or erase operations
s
Embedded Erase Algorithms
— Automatically preprograms and erases the chip
or any combination of sectors
s
Embedded Program Algorithms
— Automatically programs and verifies data at
specified address
s
Data Polling and Toggle Bit feature for detection
of program or erase cycle completion
s
Erase suspend/resume
— Supports reading data from a sector not being
erased
s
Low power consumption
— 20 mA typical active read current
— 30 mA typical program/erase current
s
Enhanced power management for standby
mode
— <1
µA
typical standby current
— Standard access time from standby mode
GENERAL DESCRIPTION
The Am29F040 is a 4 Mbit, 5.0 Volt-only Flash memory
organized as 512 Kbytes of 8 bits each. The Am29F040
is offered in a 32-pin package. This device is designed
to be programmed in-system with the standard system
5.0 V V
CC
supply. A 12.0 V V
PP
is not required for
write or erase operations. The device can also be
reprogrammed in standard EPROM programmers.
The standard Am29F040 offers access times between
55 ns and 150 ns, allowing operation of high-speed
microprocessors without wait states. To eliminate bus
contention the device has separate chip enable (CE),
write enable (WE) and output enable (OE) controls.
The Am29F040 is entirely command set compatible
with the JEDEC single-power-supply Flash standard.
Commands are written to the command register using
standard microprocessor write timings. Register con-
tents serve as input to an internal state machine
which controls the erase and programming circuitry.
Write cycles also internally latch addresses and data
needed for the programming and erase operations.
Reading data out of the device is similar to reading
from 12.0 Volt Flash or EPROM devices.
The Am29F040 is programmed by executing the pro-
gram command sequence. This will invoke the Embed-
ded Program Algorithm which is an internal algorithm
that automatically times the program pulse widths and
verifies proper cell margin. Typically, each sector can
be programmed and verified in less than one second.
Erase is accomplished by executing the erase com-
mand sequence. This will invoke the Embedded Erase
Algorithm which is an internal algorithm that automati-
cally preprograms the array if it is not already pro-
grammed before executing the erase operation. During
erase, the device automatically times the erase pulse
widths and verifies proper cell margin.
Publication#
17113
Rev:
E
Amendment/0
Issue Date:
November 1996
Any individual sector is typically erased and verified in
1.0 seconds (if already completely preprogrammed).
This device also features a sector erase architecture.
The sector mode allows for 64K byte blocks of memory
to be erased and reprogrammed without affecting
other blocks. The Am29F040 is erased when shipped
from the factory.
The device features single 5.0 V power supply opera-
tion for both read and write functions. Internally gener-
ated and regulated voltages are provided for the
program and erase operations. A low V
CC
detector
automatically inhibits write operations on the loss of
power. The end of program or erase is detected by Data
Polling of DQ7 or by the Toggle Bit feature on DQ6.
Once the end of a program or erase cycle has been
completed, the device internally resets to the read
mode.
AMD’s Flash technology combines years of EPROM
and E
2
PROM experience to produce the highest levels
of quality, reliability and cost effectiveness. The
Am29F040 memory electrically erases the entire chip
or all bits within a sector simultaneously via Fowler-
Nordheim tunneling. The bytes are programmed one
byte at a time using the EPROM programming
mechanism of hot electron injection.
Flexible Sector-Erase Architecture
s
Eight 64 Kbyte sectors
s
Individual-sector, multiple-sector, or bulk-erase
capability
s
Individual or multiple-sector protection is user
definable
7FFFFh
6FFFFh
5FFFFh
64 Kbytes per Sector
4FFFFh
3FFFFh
2FFFFh
1FFFFh
0FFFFh
00000h
17113E-1
2
Am29F040
PRODUCT SELECTOR GUIDE
Family Part No:
Ordering Part No: V
CC
= 5.0 V
±
5%
V
CC
= 5.0 V
±
10%
Max Access Time (ns)
CE (E) Access (ns)
OE (G) Access (ns)
55
55
25
-55
-70
70
70
30
-90
90
90
35
-120
120
120
50
-150
150
150
55
Am29F040
BLOCK DIAGRAM
DQ0–DQ7
V
CC
V
SS
Erase Voltage
Generator
Input/Output
Buffers
WE
State
Control
Command
Register
PGM Voltage
Generator
Chip Enable
Output Enable
Logic
STB
Data Latch
CE
OE
STB
V
CC
Detector
Timer
Address Latch
Y-Decoder
Y-Gating
X-Decoder
Cell Matrix
A0–A18
17113E-2
Am29F040
3
CONNECTION DIAGRAMS
PDIP
A18
A16
A15
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
V
SS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
V
CC
V
CC
A12
A15
A16
A18
A17
A14
A13
A8
A9
A11
OE
A10
CE
DQ7
DQ6
DQ5
DQ4
DQ3
17113E-3
17113E-4
PLCC
4
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
5
6
7
8
9
10
11
12
13
3
2
1 32 31 30
29
28
27
26
25
24
23
22
21
A14
A13
A8
A9
A11
OE
A10
CE
DQ7
14 15 16 17 18 19 20
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
OE
A10
CE
DQ7
DQ6
DQ5
DQ4
DQ3
V
SS
DQ2
DQ1
DQ0
A0
A1
A2
A3
A11
A9
A8
A13
A14
A17
WE
V
CC
A18
A16
A15
A12
A7
A6
A5
A4
17113E-5
TSOP
A11
A9
A8
A13
A14
A17
WE
V
CC
A18
A16
A15
A12
A7
A6
A5
A4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
29F040 Standard Pinout
OE
A10
CE
DQ7
DQ6
DQ5
DQ4
DQ3
V
SS
DQ2
DQ1
DQ0
A0
A1
A2
A3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
29F040 Reverse Pinout
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
4
Am29F040
V
SS
A17
WE
WE
PIN CONFIGURATION
A0–A18
= Address Inputs
DQ0–DQ7 = Data Input/Output
CE
OE
WE
V
SS
V
CC
= Chip Enable
= Output Enable
= Write Enable
= Device Ground
= Device Power Supply
(5.0 V
±10%
or
±5%)
LOGIC SYMBOL
19
A0–A18
DQ0–DQ7
CE (E)
OE (G)
WE (W)
8
17113E-6
Am29F040
5
