PRELIMINARY
Am29F400AT/Am29F400AB
4 Megabit (524,288 x 8-Bit/262,144 x 16-Bit) CMOS 5.0 Volt-only,
Sector Erase Flash Memory
DISTINCTIVE CHARACTERISTICS
s
5.0 V
±
10% for read and write operations
— Minimizes system level power requirements
s
Compatible with JEDEC-standards
— Pinout and software compatible with
single-power-supply flash
— Superior inadvertent write protection
s
Package options
— 44-pin SO
— 48-pin TSOP
s
Minimum 100,000 write/erase cycles guaranteed
s
High performance
— 60 ns maximum access time
s
Sector erase architecture
— One 16 Kbyte, two 8 Kbytes, one 32 Kbyte, and
seven 64 Kbytes
— Any combination of sectors can be erased. Also
supports full chip erase.
s
Sector protection
— Hardware method that disables any combination
of sectors from write or erase operations.
Implemented using standard PROM
programming equipment.
s
Embedded Erase
™
Algorithms
— Automatically preprograms and erases the chip
or any sector
s
Embedded Program
™
Algorithms
— Automatically programs and verifies data at
specified address
s
Data Polling and Toggle Bit feature for detection
of program or erase cycle completion
s
Ready/Busy output (RY/BY)
— Hardware method for detection of program or
erase cycle completion
s
Erase Suspend/Resume
— Supports reading data from a sector not being
erased
s
Low power consumption
— 20 mA typical active read current for Byte Mode
— 28 mA typical active read current for Word Mode
— 30 mA typical program/erase current
s
Enhanced power management for standby
mode
— 1
µ
A typical standby current
s
Boot Code Sector Architecture
— T = Top sector
— B = Bottom sector
s
Hardware RESET pin
— Resets internal state machine to the read mode
5.0 V-only Flash
GENERAL DESCRIPTION
The Am29F400A is a 4 Mbit, 5.0 Volt-only Flash memory
organized as 512 Kbytes of 8 bits each or 256 Kwords
of 16 bits each. The 4 Mbits of data is divided into 11
sectors of one 16 Kbyte, two 8 Kbyte, one 32 Kbyte,
and seven 64 Kbytes, for flexible erase capability. The
8 bits of data will appear on DQ0–DQ7 or 16 bits on
DQ0–DQ15. The Am29F400A is offered in 44-pin SO
and 48-pin TSOP packages. This device is designed
to be programmed in-system with the standard system
5.0 Volt V
CC
supply. 12.0 Volt V
PP
is not required for
program or erase operations. The device can also be re-
programmed in standard EPROM programmers.
The standard Am29F400A offers access times of
60 ns, 70 ns, 90 ns, 120 ns and 150 ns, allowing high
speed microprocessors to operate without wait states.
To eliminate bus contention the device has sepa-
rate chip enable (CE), write enable (WE) and output
enable (OE) controls.
The Am29F400A is entirely command set compatible
with the JEDEC single-power-supply Flash standard.
Commands are written to the command register using
standard microprocessor write timings. Register con-
tents serve as input to an internal state-machine
which controls the erase and programming circuitry.
Publication#
20380
Rev:
B
Amendment/0
Issue Date:
April 1997
This document contains information on a product under development at Advanced Micro Devices. The information
is intended to help you evaluate this product. AMD reserves the right to change or discontinue work on this proposed
product without notice.
P R E L I M I N A R Y
Write cycles also internally latch addresses and data
needed for the programming and erase operations.
Reading data out of the device is similar to reading
from 12.0 Volt Flash or EPROM devices.
The Am29F400A is programmed by executing the pro-
gram command sequence. This will invoke the Embed-
ded Program Algorithm which is an internal algorithm
that automatically times the program pulse widths and
verifies proper cell margin. Erase is accomplished by
executing the erase command sequence. This
will invoke the Embedded Erase Algorithm which is an
internal algorithm that automatically preprograms the
array if it is not already programmed before executing
the erase operation. During erase, the device automat-
ically times the erase pulse widths and verifies proper
cell margin.
This device also features a sector erase architecture.
This allows for sectors of memory to be erased and re-
programmed without affecting the data contents of
other sectors. A sector is typically erased and verified
within 1.5 seconds. The Am29F400A is erased when
shipped from the factory.
The Am29F400A device also features hardware sector
protection. This feature will disable both program and
erase operations in any combination of eleven sectors
of memory.
AMD has implemented an Erase Suspend feature that
enables the user to put erase on hold for any period of
time to read data from a sector that was not being
erased. Thus, true background erase can be achieved.
The device features single 5.0 Volt power supply oper-
ation for both read and write functions. Internally gen-
erated and regulated voltages are provided for the
program and erase operations. A low V
CC
detector au-
tomatically inhibits write operations during power tran-
sitions. The end of program or erase is detected by the
RY/BY pin. Data Polling of DQ7, or by the Toggle Bit
(DQ6). Once the end of a program or erase cycle has
been completed, the device automatically resets to the
read mode.
The Am29F400A also has a hardware RESET pin.
When this pin is driven low, execution of any Embed-
ded Program Algorithm or Embedded Erase Algorithm
will be terminated. The internal state machine will then
be reset into the read mode. The RESET pin may be
tied to the system reset circuitry. Therefore, if a system
reset occurs during the Embedded Program Algorithm
or Embedded Erase Algorithm, the device will be auto-
matically reset to the read mode and will have errone-
ous data stored in the address locations being
operated on. These locations will need rewriting after
the Reset. Resetting the device will enable the sys-
tem’s microprocessor to read the boot-up firmware
from the Flash memory.
AMD’s Flash technology combines years of Flash
memory manufacturing experience to produce the
highest levels of quality, reliability and cost effective-
ness. The Am29F400A memory electrically erases all
b i t s w i t h i n a s e c t o r s i mu l t a n e o u s l y v i a
Fowler-Nordhiem tunneling. The bytes/words are pro-
grammed one byte/word at a time using the EPROM
programming mechanism of hot electron injection.
Flexible Sector-Erase Architecture
s
One 16 Kbyte, two 8 Kbytes, one 32 Kbyte, and
seven 64 Kbyte sectors
s
Individual-sector or multiple-sector erase capability
s
Sector protection is user definable
(x8)
SA10
SA9
SA8
SA7
SA6
SA5
SA4
SA3
SA2
SA1
SA0
16 Kbyte
8 Kbyte
8 Kbyte
32 Kbyte
64 Kbyte
64 Kbyte
64 Kbyte
64 Kbyte
64 Kbyte
64 Kbyte
64 Kbyte
6FFFFh 37FFFh
5FFFFh 2FFFFh
4FFFFh 27FFFh
3FFFFh 1FFFFh
2FFFFh 17FFFh
1FFFFh 0FFFFh
0FFFFh 07FFFh
00000h
00000h
20380B-1
(x16)
7FFFFh 3FFFFh
7BFFFh 3DFFFh
79FFFh 3CFFFh
77FFFh 3BFFFh
Am29F400AT Sector Architecture
(x8)
SA10
SA9
SA8
SA7
SA6
SA5
SA4
SA3
SA2
SA1
SA0
64 Kbyte
64 Kbyte
64 Kbyte
64 Kbyte
64 Kbyte
64 Kbyte
64 Kbyte
32 Kbyte
8 Kbyte
8 Kbyte
16 Kbyte
05FFFh 02FFFh
03FFFh 01FFFh
00000h
00000h
20380B-2
(x16)
7FFFFh 3FFFFh
6BFFFh 37FFFh
5FFFFh 2FFFFh
4FFFFh 27FFFh
3FFFFh 1FFFFh
2FFFFh 17FFFh
1FFFFh 0FFFFh
0FFFFh 07FFFh
07FFFh 03FFFh
Am29F400AB Sector Architecture
2
Am29F400AT/Am29F400AB
P R E L I M I N A R Y
PRODUCT SELECTOR GUIDE
Family Part No:
Ordering Part No:V
CC
= 5.0 V
±
5
%
V
CC
= 5.0 V
±
10%
Max Access Time (ns)
CE (E) Access (ns)
OE (G) Access (ns)
60
60
30
-65
-70
70
70
30
-90
90
90
35
-120
120
120
50
-150
150
150
55
Am29F400A
BLOCK DIAGRAM
5.0 V-only Flash
DQ0–DQ15
V
CC
V
SS
RY/BY
Buffer
RY/BY
Erase Voltage
Generator
Input/Output
Buffers
WE
BYTE
RESET
State
Control
Command
Register
PGM Voltage
Generator
Chip Enable
Output Enable
Logic
STB
Data
Latch
CE
OE
STB
V
CC
Detector
Timer
Address Latch
Y-Decoder
Y-Gating
X-Decoder
Cell Matrix
A0-A17
A-1
20380B-3
Am29F400AT/Am29F400AB
3
P R E L I M I N A R Y
CONNECTION DIAGRAMS
SO
NC
RY/BY
A17
A7
A6
A5
A4
A3
A2
A1
A0
CE
VSS
OE
DQ0
DQ8
DQ1
DQ9
DQ2
DQ10
DQ3
DQ11
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
RESET
WE
A8
A9
A10
A11
A12
A13
A14
A15
A16
BYTE
VSS
DQ15/A-1
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
VCC
20380B-4
4
Am29F400AT/Am29F400AB
P R E L I M I N A R Y
CONNECTION DIAGRAMS
A15
A14
A13
A12
A11
A10
A9
A8
NC
NC
WE
RESET
NC
NC
RY/BY
NC
A17
A7
A6
A5
A4
A3
A2
A1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
A16
BYTE
VSS
DQ15/A-1
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
VCC
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE
VSS
CE
A0
20380B-5
5.0 V-only Flash
Standard TSOP
A16
BYTE
VSS
DQ15/A-1
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
VCC
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE
VSS
CE
A0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
A15
A14
A13
A12
A11
A10
A9
A8
NC
NC
WE
RESET
NC
NC
RY/BY
NC
A17
A7
A6
A5
A4
A3
A2
A1
20380B-6
Reverse TSOP
Am29F400AT/Am29F400AB
5
FPGA/CPLD
