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Am29LV001B

Data Sheet

RETIRED

PRODUCT

This product has been retired and is not recommended for designs. Please contact your Spansion

representative for alternates. Availability of this document is retained for reference and historical

purposes only.

The following document contains information on Spansion memory products.

Continuity of Specifications

There is no change to this data sheet as a result of offering the device as a Spansion product. Any

changes that have been made are the result of normal data sheet improvement and are noted in the

document revision summary.

For More Information

Please contact your local sales office for additional information about Spansion memory solutions.

Publication Number

21553

Revision

Amendment

Issue Date

May 5, 2006

THIS PAGE LEFT INTENTIONALLY BLANK.

DATA SHEET

Am29LV001B

1 Megabit (128 K x 8-Bit)

CMOS 3.0 Volt-only Boot Sector Flash Memory

This product has been retired and is not recommended for designs. Please contact your Spansion representative for alternates. Availability of this document is retained for reference and

historical purposes only.

DISTINCTIVE CHARACTERISTICS

■

Single power supply operation

— Full voltage range: 2.7 to 3.6 volt read and write

operations for battery-powered applications

— Regulated voltage range: 3.0 to 3.6 volt read and

write operations and for compatibility with high

performance 3.3 volt microprocessors

■

Manufactured on 0.32 µm process technology

■

High performance

— Full voltage range: access times as fast as 55 ns

— Regulated voltage range: access times as fast as

45 ns

■

Ultra low power consumption (typical values at 5

MHz)

— 200 nA Automatic Sleep mode current

— 200 nA standby mode current

— 7 mA read current

— 15 mA program/erase current

■

Flexible sector architecture

— One 8 Kbyte, two 4 Kbyte, and seven 16 Kbyte

— Supports full chip erase

— Sector Protection features:

Hardware method of locking a sector to prevent any

program or erase operations within that sector

Sectors can be locked in-system or via

programming equipment

Temporary Sector Unprotect feature allows code

changes in previously locked sectors

■

Unlock Bypass Mode Program Command

— Reduces overall programming time when issuing

multiple program command sequences

■

Top or bottom boot block configurations available

■

Embedded Algorithms

— Embedded Erase algorithm automatically

preprograms and erases the entire chip or any

combination of designated sectors

— Embedded Program algorithm automatically

writes and verifies data at specified addresses

■

Minimum 1 million erase cycle guarantee per sector

■

20 Year data retention at 125°C

— Reliable operation for the life of the system

■

Package option

— 32-pin TSOP

— 32-pin PLCC

■

Compatibility with JEDEC standards

— Pinout and software compatible with single-

power supply Flash

— Superior inadvertent write protection

■

Data# Polling and toggle bits

— Provides a software method of detecting program

or erase operation completion

■

Erase Suspend/Erase Resume

— Supports reading data from or programming data

to a sector that is not being erased

■

Hardware reset pin (RESET#)

— Hardware method for resetting the device to

reading array data

This Data Sheet states AMD’s current technical specifications regarding the Products described herein. This Data

Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.

Publication#

21557

Rev:

Amendment:

Issue Date:

May 5, 2006

DATA SHEET

GENERAL DESCRIPTION

The Am29LV001B is a 1 Mbit, 3.0 Volt-only Flash

memory device organized as 131,072 bytes. The

Am29LV001B has a boot sector architecture.

The device is offered in 32-pin PLCC and 32-pin TSOP

packages. The byte-wide (x8) data appears on DQ7-DQ0.

All read, erase, and program operations are accomplished

using only a single power supply. The device can also be

programmed in standard EPROM programmers.

The standard Am29LV001B offers access times of 45,

55, 70, and 90 ns, allowing high speed microprocessors

to operate without wait states. To eliminate bus contention,

the device has separate chip enable (CE#), write enable

(WE#) and output enable (OE#) controls.

The device requires only a single power supply (2.7 V–3.6V)

for both read and write functions. Internally generated and

regulated voltages are provided for the program and

erase operations.

The Am29LV001B is entirely command set compatible

with the JEDEC single-power-supply Flash standard.

Commands are written to the command register using

standard microprocessor write timings. Register con-

tents serve as input to an internal state-machine that

controls the erase and programming circuitry. Write

cycles also internally latch addresses and data needed

for the programming and erase operations. Reading

data out of the device is similar to reading from other

Flash or EPROM devices.

Device programming occurs by executing the program

command sequence. This initiates the Embedded

Program algorithm—an internal algorithm that automatically

times the program pulse widths and verifies proper cell

margin. The Unlock Bypass mode facilitates faster pro-

gramming times by requiring only two write cycles to

program data instead of four.

Device erasure occurs by executing the erase command

sequence. This initiates the Embedded Erase algorithm—

an internal algorithm that automatically preprograms the

array (if it is not already programmed) before executing the

erase operation. During erase, the device automatically

times the erase pulse widths and verifies proper cell margin.

The host system can detect whether a program or

erase operation is complete by reading the DQ7 (Data#

Polling) and DQ6 (toggle) status bits. After a program

or erase cycle has been completed, the device is ready

to read array data or accept another command.

The sector erase architecture allows memory sectors

to be erased and reprogrammed without affecting the

data contents of other sectors. The device is fully

erased when shipped from the factory.

Hardware data protection measures include a low VCC

detector that automatically inhibits write operations during

power transitions. The hardware sector protection feature

disables both program and erase operations in any com-

bination of the sectors of memory. This can be achieved

in-system or via programming equipment.

The Erase Suspend feature enables the user to put

erase on hold for any period of time to read data from,

or program data to, any sector that is not selected for

erasure. True background erase can thus be achieved.

The hardware RESET# pin terminates any operation in

progress and resets the internal state machine to

reading array data. The RESET# pin may be tied to the

system reset circuitry. A system reset would thus also

reset the device, enabling the system microprocessor

to read the boot-up firmware from the Flash memory.

The device offers two power-saving features. When

addresses are stable for a specified amount of time, the

device enters the automatic sleep mode. The system can

also place the device into the standby mode. Power con-

sumption is greatly reduced in both these modes.

AMD’s Flash technology combines years of Flash

memory manufacturing experience to produce the highest

levels of quality, reliability and cost effectiveness. The

device electrically erases all bits within a sector simulta-

neously via Fowler-Nordheim tunneling. The data is

programmed using hot electron injection.

Am29LV001B

21557F4 May 5, 2006

DATA SHEET

TABLE OF CONTENTS

Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 4

Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . . 5

Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 6

Device Bus Operations . . . . . . . . . . . . . . . . . . . . . . 7

Table 1. Am29LV001B Device Bus Operations ................................ 7

DQ6: Toggle Bit I .................................................................... 18

DQ2: Toggle Bit II ................................................................... 19

Reading Toggle Bits DQ6/DQ2 ............................................... 19

DQ5: Exceeded Timing Limits ................................................ 19

Figure 6. Toggle Bit Algorithm ........................................................ 20

DQ3: Sector Erase Timer ....................................................... 20

Table 6. Write Operation Status..................................................... 21

Absolute Maximum Ratings . . . . . . . . . . . . . . . . 22

Figure 7. Maximum Negative Overshoot Waveform ...................... 22

Figure 8. Maximum Positive Overshoot Waveform ........................ 22

Requirements for Reading Array Data ..................................... 7

Writing Commands/Command Sequences .............................. 7

Program and Erase Operation Status ...................................... 8

Standby Mode .......................................................................... 8

Automatic Sleep Mode ............................................................. 8

RESET#: Hardware Reset Pin ................................................. 8

Output Disable Mode ................................................................ 8

Table 2. Am29LV001B Top Boot Sector Architecture ...................... 9

Table 3. Am29LV001B Bottom Boot Sector Architecture.................. 9

Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . 22

DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 23

Figure 9. I

CC1

Current vs. Time (Showing Active and Automatic

Sleep Currents) .............................................................................. 24

Figure 10. Typical I

CC1

vs. Frequency ........................................... 24

Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Figure 11. Test Setup ..................................................................... 25

Table 7. Test Specifications ........................................................... 25

Autoselect Mode ....................................................................... 9

Table 4. Am29LV001B Autoselect Codes....................................... 10

Key to Switching Waveforms. . . . . . . . . . . . . . . . 25

Figure 12. Input Waveforms and Measurement Levels ................. 25

Sector Protection/Unprotection ............................................... 10

Temporary Sector Unprotect .................................................. 10

Figure 1. In-System Sector Protect/Unprotect Algorithms ...............11

Figure 2. Temporary Sector Unprotect Operation ...........................12

AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 26

Figure 13. Read Operations Timings ............................................. 26

Hardware Reset (RESET#) .................................................... 27

Figure 14. RESET# Timings .......................................................... 27

Hardware Data Protection ...................................................... 12

Low V

Write Inhibit .............................................................. 12

Write Pulse “Glitch” Protection ............................................... 12

Logical Inhibit .......................................................................... 12

Power-Up Write Inhibit ............................................................ 12

Command Definitions . . . . . . . . . . . . . . . . . . . . . . 13

Reading Array Data ................................................................ 13

Reset Command ..................................................................... 13

Autoselect Command Sequence ............................................ 13

Byte Program Command Sequence ....................................... 13

Unlock Bypass Command Sequence ..................................... 14

Figure 3. Program Operation ..........................................................14

Erase/Program Operations ..................................................... 28

Figure 15. Program Operation Timings .......................................... 29

Figure 16. Chip/Sector Erase Operation Timings .......................... 30

Figure 17. Data# Polling Timings (During Embedded Algorithms) . 31

Figure 18. Toggle Bit Timings (During Embedded Algorithms) ...... 31

Figure 19. DQ2 vs. DQ6 ................................................................. 32

Temporary Sector Unprotect .................................................. 32

Figure 20. Temporary Sector Unprotect Timing Diagram .............. 32

Figure 21. In-System Sector Protect/Unprotect Timing Diagram ... 33

Alternate CE# Controlled Erase/Program Operations ............ 34

Figure 22. Alternate CE# Controlled Write Operation Timings ...... 35

Chip Erase Command Sequence ........................................... 14

Sector Erase Command Sequence ........................................ 15

Erase Suspend/Erase Resume Commands ........................... 15

Figure 4. Erase Operation ...............................................................16

Command Definitions ............................................................. 17

Table 5. Am29LV001B Command Definitions ................................ 17

Write Operation Status . . . . . . . . . . . . . . . . . . . . . 18

DQ7: Data# Polling ................................................................. 18

Figure 5. Data# Polling Algorithm ...................................................18

Erase and Programming Performance . . . . . . . 36

Latchup Characteristics . . . . . . . . . . . . . . . . . . . . 36

TSOP Pin Capacitance . . . . . . . . . . . . . . . . . . . . . 36

PLCC Pin Capacitance . . . . . . . . . . . . . . . . . . . . . 36

Data Retention. . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 38

PL 032—32-Pin Plastic Leaded Chip Carrier ......................... 38

TS 032—32-Pin Standard Thin Small Outline Package ......... 39

Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 40

May 5, 2006 21557F4

Am29LV001B