ADVANCE INFORMATION
Am29LV065M
64 Megabit (8 M x 8-Bit) MirrorBit™ 3.0 Volt-only
Uniform Sector Flash Memory with VersatileI/O™ Control
DISTINCTIVE CHARACTERISTICS
ARCHITECTURAL ADVANTAGES
s
Single power supply operation
— 2.7–3.6 volt read, erase, and program operations
s
Enhanced VersatileI/O™ control
— Device generates data output voltages and tolerates
data input voltages as determined by the voltage on
the V
IO
pin; operates from 1.65 to 3.6 V
s
Manufactured on 0.23 µm MirrorBit process
technology
s
SecSi™ (Secured Silicon) Sector region
— 256-byte sector for permanent, secure identification
through an 16-byte random Electronic Serial Number,
accessible through a command sequence
— May be programmed and locked at the factory or by
the customer
s
Flexible sector architecture
— One hundred twenty-eight 64 Kbyte sectors
s
Compatibility with JEDEC standards
— Provides pinout and software compatibility for
single-power supply flash, and superior inadvertent
write protection
s
Minimum 100,000 erase cycle guarantee per sector
s
20-year data retention at 125°C
PERFORMANCE CHARACTERISTICS
s
High performance
— 90 ns access time
— 25 ns page read times
— 1 s typical sector erase time
— 3.0 µs typical write buffer byte programming time:
32-byte write buffer reduces overall programming
time for multiple-byte updates
— 8-byte read page buffer
— 32-byte write buffer
s
Low power consumption (typical values at 3.0 V,
5 MHz)
— 30 mA typical active read current
— 50 mA typical erase/program current
— 1 µA typical standby mode current
s
Package options
— 48-pin TSOP
— 63-ball FBGA
SOFTWARE & HARDWARE FEATURES
s
Software features
— Program Suspend & Resume: read other sectors
before programming operation is completed
— Erase Suspend & Resume: read/program other
sectors before an erase operation is completed
— Data# polling & toggle bits provide status
— Unlock Bypass Program command reduces overall
multiple-byte programming time
— CFI (Common Flash Interface) compliant: allows host
system to identify and accommodate multiple flash
devices
s
Hardware features
— Sector Group Protection: hardware method of
preventing write operations within a sector group
— Temporary Sector Unprotect: V
ID
-level method of
changing code in locked sectors
— ACC (high voltage) pin accelerates programming
time for higher throughput during system production
— Hardware reset pin (RESET#) resets device
— Ready/Busy# pin (RY/BY#) detects program or erase
cycle completion
This Data Sheet states AMD’s current technical specifications regarding the Products described herein. This Data
Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
Publication#
25262
Rev:
A
Amendment/0
Issue Date:
August 3, 2001
Refer to AMD’s Website (www.amd.com) for the latest information.
A D V A N C E
I N F O R M A T I O N
GENERAL DESCRIPTION
The Am29LV065M is a 64 Mbit, 3.0 volt (3.0 V to 3.6
V) single power supply flash memory devices orga-
nized as 8,388,608 bytes. The device has an 8-bit
wide data bus, and can be programmed either in the
host system or in standard EPROM programmers.
An access time of 90 ns is available for applications
where V
IO
≥
3.0 V. An access time of 100 ns is avail-
able for applications where V
IO
< 3.0 V. The device is
offered in a 48-pin TSOP or 63-ball FBGA package.
Each device has separate chip enable (CE#), write en-
able (WE#) and output enable (OE#) controls.
Each device requires only a
single 3.0 volt power
supply
(2.7 V to 3.6 V) for both read and write func-
tions. In addition to a V
CC
input, a high-voltage
accel-
erated program (ACC )
input provides shor ter
programming times through increased current. This
feature is intended to facilitate factory throughput dur-
ing system production, but may also be used in the
field if desired.
The device is entirely command set compatible with
the
JEDEC single-power-supply Flash standard.
Commands are written to the device using standard
microprocessor write timing. Write cycles also inter-
nally latch addresses and data needed for the pro-
gramming and erase operations.
The
sector erase architecture
allows memory sec-
tors to be erased and reprogrammed without affecting
the data contents of other sectors. The device is fully
erased when shipped from the factory.
Device programming and erasure are initiated through
command sequences. Once a program or erase oper-
ation has begun, the host system need only poll the
DQ7 (Data# Polling) or DQ6 (toggle)
status bits
or
monitor the
Ready/Busy# (RY/BY#)
output to deter-
mine whether the operation is complete. To facilitate
programming, an
Unlock Bypass
mode reduces com-
mand sequence overhead by requiring only two write
cycles to program data instead of four.
The
VersatileI/O™
(V
IO
) control allows the host sys-
tem to set the voltage levels that the device generates
at its data outputs and the voltages tolerated at its data
inputs to the same voltage level that is asserted on the
V
IO
pin. This allows the device to operate in a 1.8 V or
3 V system environment as required.
Hardware data protection
measures include a low
V
CC
detector that automatically inhibits write opera-
tions during power transitions. The hardware sector
protection feature disables both program and erase
operations in any combination of sectors of memory.
This can be achieved in-system or via programming
equipment.
The
Erase Suspend/Erase Resume
feature allows
the host system to pause an erase operation in a given
sector to read or program any other sector and then
complete the erase operation. The
Program Sus-
pend/Program Resume
feature enables the host sys-
tem to pause a program operation in a given sector to
read any other sector and then complete the program
operation.
The
hardware RESET# pin
terminates any operation
in progress and resets the device, after which it is then
ready for a new operation. The RESET# pin may be
tied to the system reset circuitry. A system reset would
thus also reset the device, enabling the host system to
read boot-up firmware from the Flash memory device.
The device reduces power consumption in the
standby mode
when it detects specific voltage levels
on CE# and RESET#, or when addresses have been
stable for a specified period of time.
The
SecSi™ (Secured Silicon) Sector
provides a 256
byte area for code or data that can be permanently
protected. Once this sector is protected, no further
changes within the sector can occur.
AMD MirrorBit flash technology combines years of
Flash memory manufacturing experience to produce
the highest levels of quality, reliability and cost effec-
tiveness. The device electrically erases all bits within a
sector simultaneously via hot-hole assisted erase. The
data is programmed using hot electron injection.
2
Am29LV065M
A D V A N C E
I N F O R M A T I O N
PRODUCT SELECTOR GUIDE
Part Number
Speed Option
Max. Access Time (ns)
Max. CE# Access Time (ns)
Max. Page access time (t
PACC
)
Max. OE# Access Time (ns)
V
CC
= 2.7–3.6 V all devices
90
(V
IO
= 3.0–3.6 V)
90
90
25
25
Am29LV065M
101
(V
IO
= 2.7–3.0 V)
100
100
30
30
102
(V
IO
= 1.65–2.7 V)
100
100
40
40
BLOCK DIAGRAM
RY/BY#
V
CC
V
SS
RESET#
Erase Voltage
Generator
V
IO
Input/Output
Buffers
Sector Switches
DQ0
–
DQ7
WE#
ACC
State
Control
Command
Register
PGM Voltage
Generator
Chip Enable
Output Enable
Logic
STB
Data
Latch
CE#
OE#
STB
V
CC
Detector
Timer
Address Latch
Y-Decoder
Y-Gating
X-Decoder
Cell Matrix
A22–A0
Am29LV065M
3
A D V A N C E
I N F O R M A T I O N
CONNECTION DIAGRAMS
NC
A22
A16
A15
A14
A13
A12
A11
A9
A8
WE#
RESET#
ACC
RY/BY#
A18
A7
A6
A5
A4
A3
A2
A1
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48-Pin Standard TSOP
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
NC
NC
A17
V
SS
A20
A19
A10
DQ7
DQ6
DQ5
DQ4
V
CC
V
IO
A21
DQ3
DQ2
DQ1
DQ0
OE#
V
SS
CE#
A0
NC
NC
NC
NC
A17
V
SS
A20
A19
A10
DQ7
DQ6
DQ5
DQ4
V
CC
V
IO
A21
DQ3
DQ2
DQ1
DQ0
OE#
V
SS
CE#
A0
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48-Pin Reverse TSOP
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
NC
A22
A16
A15
A14
A13
A12
A11
A9
A8
WE#
RESET#
ACC
RY/BY#
A18
A7
A6
A5
A4
A3
A2
A1
NC
NC
4
Am29LV065M
A D V A N C E
I N F O R M A T I O N
CONNECTION DIAGRAMS
63-Ball FBGA
Top View, Balls Facing Down
A8
NC*
A7
NC*
B8
NC*
B7
NC*
C7
A14
C6
A9
C5
WE#
C4
RY/BY#
C3
A7
D7
A13
D6
A8
D5
RESET#
D4
ACC
D3
A18
D2
A4
E7
A15
E6
A11
E5
A22
E4
NC
E3
A6
E2
A2
F7
A16
F6
A12
F5
NC
F4
NC
F3
A5
F2
A1
G7
A17
G6
A19
G5
DQ5
G4
DQ2
G3
DQ0
G2
A0
H7
NC
H6
A10
H5
NC
H4
DQ3
H3
NC
H2
CE#
J7
A20
J6
DQ6
J5
V
CC
J4
V
IO
J3
NC
J2
OE#
K7
V
SS
K6
DQ7
K5
DQ4
K4
A21
K3
DQ1
K2
V
SS
L8
NC*
L7
NC*
M8
NC*
M7
NC*
A2
NC*
A1
NC*
B1
NC*
C2
A3
L2
NC*
L1
M2
NC*
M1
NC*
* Balls are shorted together via the substrate but not connected to the die.
NC*
Special Handling Instructions for FBGA
Package
Special handling is required for Flash Memory products
in FBGA packages.
Flash memory devices in FBGA packages may be
damaged if exposed to ultrasonic cleaning methods.
The package and/or data integrity may be compromised
if the package body is exposed to temperatures above
150°C for prolonged periods of time.
Am29LV065M
5
嵌入式系统
