ADVANCE INFORMATION
Am29LV256M
256 Megabit (16 M x 16-Bit/32 M x 8-Bit) MirrorBit 3.0 Volt-only
Uniform Sector Flash Memory with VersatileI/O Control
DISTINCTIVE CHARACTERISTICS
ARCHITECTURAL ADVANTAGES
s
Single power supply operation
— 3 volt read, erase, and program operations
s
VersatileI/O control
— Device generates and tolerates voltages on CE# and
DQ I/Os as determined by the voltage on the V
IO
pin;
operates from 1.65 to 3.6 V
s
Manufactured on 0.23 µm MirrorBit process
technology
s
SecSi (Secured Silicon) Sector region
— 128-word/256-byte sector for permanent, secure
identification through an 8-word/16-byte random
Electronic Serial Number, accessible through a
command sequence
— May be programmed and locked at the factory or by
the customer
s
Flexible sector architecture
— Five hundred twelve 32 Kword (64 Kbyte) sectors
s
Compatibility with JEDEC standards
— Provides pinout and software compatibility for
single-power supply flash, and superior inadvertent
write protection
s
Minimum 100,000 erase cycle guarantee per sector
s
20-year data retention at 125°C
PERFORMANCE CHARACTERISTICS
s
High performance
— 90 ns access time
— 25 ns page read times
— 0.4 s typical sector erase time
— 5.9 µs typical write buffer word programming time:
16-word/32-byte write buffer reduces overall
programming time for multiple-word updates
— 4-word/8-byte page read buffer
— 16-word/32-byte write buffer
s
Low power consumption (typical values at 3.0 V, 5
MHz)
— 30 mA typical active read current
— 50 mA typical erase/program current
— 1 µA typical standby mode current
s
Package options
— 56-pin TSOP
— 64-ball Fortified BGA
SOFTWARE & HARDWARE FEATURES
s
Software features
— Program Suspend & Resume: read other sectors
before programming operation is completed
— Erase Suspend & Resume: read/program other
sectors before an erase operation is completed
— Data# polling & toggle bits provide status
— Unlock Bypass Program command reduces overall
multiple-word or byte programming time
— CFI (Common Flash Interface) compliant: allows host
system to identify and accommodate multiple flash
devices
s
Hardware features
— Sector Group Protection: hardware-level method of
preventing write operations within a sector group
— Temporary Sector Unprotect: V
ID
-level method of
changing code in locked sectors
— WP#/ACC input accelerates programming time
(when high voltage is applied) for greater throughput
during system production. Protects first or last sector
regardless of sector protection settings
— Hardware reset input (RESET#) resets device
— Ready/Busy# output (RY/BY#) detects program or
erase cycle completion
This Data Sheet states AMD’s current technical specifications regarding the Products described herein. This Data
Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
Publication#
25263
Rev:
A
Amendment/+4
Issue Date:
April 26, 2002
Refer to AMD’s Website (www.amd.com) for the latest information.
A D V A N C E
I N F O R M A T I O N
GENERAL DESCRIPTION
The Am29LV256M is a 256 Mbit, 3.0 volt single power
supply flash memory devices organized as 16,777,216
words or 33,554,432 bytes. The device has a 16-bit
wide data bus that can also function as an 8-bit wide
data bus by using the BYTE# input. The device can be
programmed either in the host system or in standard
EPROM programmers.
An access time of 90, 100, 110, or 120 ns is available.
Note that each access time has a specific operating
voltage range (V
CC
) and an I/O voltage range (V
IO
), as
specified in the
Product Selector Guide
and the
Order-
ing Information
sections. The device is offered in a
56-pin TSOP or 64-ball Fortified BGA package. Each
device has separate chip enable (CE#), write enable
(WE#) and output enable (OE#) controls.
Each device requires only a
single 3.0 volt power
supply
for both read and write functions. In addition to
a V
CC
input, a high-voltage
accelerated program
(WP#/ACC)
input provides shorter programming times
through increased current. This feature is intended to
facilitate factory throughput during system production,
but may also be used in the field if desired.
The device is entirely command set compatible with
the
JEDEC single-power-supply Flash standard.
Commands are written to the device using standard
microprocessor write timing. Write cycles also inter-
nally latch addresses and data needed for the pro-
gramming and erase operations.
The
sector erase architecture
allows memory sec-
tors to be erased and reprogrammed without affecting
the data contents of other sectors. The device is fully
erased when shipped from the factory.
Device programming and erasure are initiated through
command sequences. Once a program or erase oper-
ation has begun, the host system need only poll the
DQ7 (Data# Polling) or DQ6 (toggle)
status bits
or
monitor the
Ready/Busy# (RY/BY#)
output to deter-
mine whether the operation is complete. To facilitate
programming, an
Unlock Bypass
mode reduces com-
mand sequence overhead by requiring only two write
cycles to program data instead of four.
The
VersatileI/O™
(V
IO
) control allows the host sys-
tem to set the voltage levels that the device generates
and tolerates voltages on the CE# and DQ I/Os to the
same voltage level that is asserted on the V
IO
pin. This
allows the device to operate in a 1.8 V or 3 V system
environment as required.
Hardware data protection
measures include a low
V
CC
detector that automatically inhibits write opera-
tions during power transitions. The hardware sector
protection feature disables both program and erase
operations in any combination of sectors of memory.
This can be achieved in-system or via programming
equipment.
The
Erase Suspend/Erase Resume
feature allows
the host system to pause an erase operation in a
given sector to read or program any other sector and
then complete the erase operation. The
Program
Suspend/Program Resume
feature enables the host
system to pause a program operation in a given sector
to read any other sector and then complete the pro-
gram operation.
The
hardware RESET# pin
terminates any operation
in progress and resets the device, after which it is then
ready for a new operation. The RESET# pin may be
tied to the system reset circuitry. A system reset would
thus also reset the device, enabling the host system to
read boot-up firmware from the Flash memory device.
The device reduces power c ons umption in the
standby mode
when it detects specific voltage levels
on CE# and RESET#, or when addresses have been
stable for a specified period of time.
The
SecSi (Secured Silicon) Sector
provides a
128-word/256-byte area for code or data that can be
permanently protected. Once this sector is protected,
no further changes within the sector can occur.
The
Write Protect (WP#/ACC)
feature protects the
first or last sector by asserting a logic low on the WP#
pin.
AMD MirrorBit flash technology combines years of
Flash memory manufacturing experience to produce
the highest levels of quality, reliability and cost effec-
tiveness. The device electrically erases all bits within a
sector simultaneously via hot-hole assisted erase. The
data is programmed using hot electron injection.
2
Am29LV256M
April 26, 2002
A D V A N C E
I N F O R M A T I O N
PRODUCT SELECTOR GUIDE
Part Number
V
CC
= 3.0–3.6 V
V
CC
= 2.7–3.6 V
Max. Access Time (ns)
Max. CE# Access Time (ns)
Max. Page access time (t
PACC
)
Max. OE# Access Time (ns)
90
90
25
25
90R
(V
IO
= 3.0–3.6 V)
(V
IO
101
= 2.7–3.6 V)
100
100
30
30
112
(V
IO
= 1.65–3.6 V)
110
110
40
40
120
(V
IO
= 1.65–3.6 V)
120
120
40
40
Am29LV256M
Speed
Option
BLOCK DIAGRAM
RY/BY#
V
CC
V
SS
V
IO
RESET#
WE#
WP#/ACC
BYTE#
Erase Voltage
Generator
Input/Output
Buffers
Sector Switches
DQ0
–
DQ15 (A-1)
State
Control
Command
Register
PGM Voltage
Generator
Chip Enable
Output Enable
Logic
STB
Data
Latch
CE#
OE#
STB
V
CC
Detector
Timer
Address Latch
Y-Decoder
Y-Gating
X-Decoder
Cell Matrix
A23–A0
April 26, 2002
Am29LV256M
3
A D V A N C E
I N F O R M A T I O N
CONNECTION DIAGRAMS
A23
A22
A15
A14
A13
A12
A11
A10
A9
A8
A19
A20
WE#
RESET#
A21
WP#/ACC
RY/BY#
A18
A17
A7
A6
A5
A4
A3
A2
A1
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
NC
NC
A16
BYTE#
V
SS
DQ15/A-1
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
V
CC
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE#
V
SS
CE#
A0
NC
V
IO
56-Pin Standard TSOP
NC
NC
A16
BYTE#
V
SS
DQ15/A-1
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
V
CC
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE#
V
SS
CE#
A0
NC
V
IO
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56-Pin Reverse TSOP
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
A23
A22
A15
A14
A13
A12
A11
A10
A9
A8
A19
A20
WE#
RESET#
A21
WP#/ACC
RY/BY#
A18
A17
A7
A6
A5
A4
A3
A2
A1
NC
NC
4
Am29LV256M
April 26, 2002
A D V A N C E
I N F O R M A T I O N
CONNECTION DIAGRAMS
64-ball Fortified BGA
Top View, Balls Facing Down
A8
NC
A7
A13
A6
A9
A5
WE#
A4
B8
A22
B7
A12
B6
A8
B5
RESET#
B4
C8
A23
C7
A14
C6
A10
C5
A21
C4
A18
C3
A6
C2
A2
C1
NC
D8
V
IO
D7
A15
D6
A11
D5
A19
D4
A20
D3
A5
D2
A1
D1
NC
E8
V
SS
E7
A16
E6
DQ7
E5
DQ5
E4
DQ2
E3
DQ0
E2
A0
E1
NC
F8
NC
F7
G8
NC
G7
H8
NC
H7
V
SS
H6
DQ6
H5
DQ4
H4
DQ3
H3
DQ1
H2
V
SS
H1
NC
BYTE# DQ15/A-1
F6
DQ14
F5
DQ12
F4
DQ10
F3
DQ8
F2
CE#
F1
V
IO
G6
DQ13
G5
V
CC
G4
DQ11
G3
DQ9
G2
OE#
G1
NC
RY/BY# WP#/ACC
A3
A7
A2
A3
A1
NC
B3
A17
B2
A4
B1
NC
Note:
The FBGA package pinout configuration shown is preliminary. The ball count and package physical dimensions have not
yet been determined. Contact AMD for further information.
Special Package Handling Instructions
Special handling is required for Flash Memory products
in molded packages (TSOP, BGA, PLCC, PDIP,
SSOP). The package and/or data integrity may be
compromised if the package body is exposed to
temperatures above 150°C for prolonged periods of
time.
April 26, 2002
Am29LV256M
5
实时操作系统RTOS
