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Am29LV400B

Data Sheet

RETIRED

PRODUCT

This product has been retired and is not available for designs. For new and current designs,

S29AL004D supersedes Am29LV400B and is the factory-recommended migration path. Please refer

to the S29AL004D datasheet for specifications and ordering information. Availability of this docu-

ment is retained for reference and historical purposes only.

The following document contains information on Spansion memory products.

Continuity of Specifications

There is no change to this data sheet as a result of offering the device as a Spansion product. Any

changes that have been made are the result of normal data sheet improvement and are noted in the

document revision summary.

For More Information

Please contact your local sales office for additional information about Spansion memory solutions.

Publication Number

21523

Revision

Amendment

Issue Date

December 4, 2006

THIS PAGE LEFT INTENTIONALLY BLANK.

DATA SHEET

Am29LV400B

4 Megabit (512 K x 8-Bit/256 K x 16-Bit)

CMOS 3.0 Volt-only Boot Sector Flash Memory

This product has been retired and is not available for designs. For new and current designs, S29AL004D supersedes Am29LV400B and is the factory-recommended migration path. Please

refer to the S29AL004D data sheet for specifications and ordering information. Availability of this document is retained for reference and historical purposes only.

DISTINCTIVE CHARACTERISTICS

■

Single power supply operation

— Full voltage range: 2.7 to 3.6 volt read and write

operations for battery-powered applications

— Regulated voltage range: 3.0 to 3.6 volt read and

write operations for compatibility with high

performance 3.3 volt microprocessors

■

Manufactured on 0.32 µm process technology

— Compatible with 0.5 µm Am29LV400 device

■

High performance

— Full voltage range: access times as fast as 70 ns

— Regulated voltage range: access times as fast as

55 ns

■

Ultra low power consumption (typical values at

5 MHz)

— 200 nA Automatic Sleep mode current

— 200 nA standby mode current

— 7 mA read current

— 15 mA program/erase current

■

Flexible sector architecture

— One 16 Kbyte, two 8 Kbyte, one 32 Kbyte, and

seven 64 Kbyte sectors (byte mode)

— One 8 Kword, two 4 Kword, one 16 Kword, and

seven 32 Kword sectors (word mode)

— Supports full chip erase

— Sector Protection features:

— A hardware method of locking a sector to prevent

any program or erase operations within that sector

— Sectors can be locked in-system or via

programming equipment

Temporary Sector Unprotect feature allows code

changes in previously locked sectors

■

Unlock Bypass Program Command

— Reduces overall programming time when issuing

multiple program command sequences

■

Top or bottom boot block configurations

available

This Data Sheet states AMD’s current technical specifications regarding the Product described herein. This Data

Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.

■

Embedded Algorithms

— Embedded Erase algorithm automatically

preprograms and erases the entire chip or any

combination of designated sectors

— Embedded Program algorithm automatically

writes and verifies data at specified addresses

■

Minimum 1,000,000 write cycle guarantee per sector

■

20-year data retention at 125°C

— Reliable operation for the life of the system

■

Package option

— 48-ball FBGA

— 48-pin TSOP

— 44-pin SO

— Lead (Pb) - Free Packaging Available

■

Compatibility with JEDEC standards

— Pinout and software compatible with

single-power supply Flash

— Superior inadvertent write protection

■

Data# Polling and toggle bits

— Provides a software method of detecting program

or erase operation completion

■

Ready/Busy# pin (RY/BY#)

— Provides a hardware method of detecting

program or erase cycle completion

■

Erase Suspend/Erase Resume

— Suspends an erase operation to read data from,

or program data to, a sector that is not being

erased, then resumes the erase operation

■

Hardware reset pin (RESET#)

— Hardware method to reset the device to reading

array data

Publication#

21523

Rev:

Amendment/4

Issue Date:

December 4, 2006

D A T A

S H E E T

GENERAL DESCRIPTION

The Am29LV400B is a 4 Mbit, 3.0 volt-only Flash

memory organized as 524,288 bytes or 262,144

words. The device is offered in 48-ball FBGA, 44-pin

SO, and 48-pin TSOP packages. The word-wide data

(x16) appears on DQ15–DQ0; the byte-wide (x8) data

appears on DQ7–DQ0. This device is designed to be

programmed in-system using only a single 3.0 volt V

supply. No V

is required for write or erase opera-

tions. The device can also be programmed in standard

EPROM programmers.

This device is manufactured using AMD’s 0.32 µm pro-

cess technology, and offers all the features and bene-

fits of the Am29LV400, which was manufactured using

0 . 5 µ m p r o c e s s t e c h n o l o gy. I n a d d i t i o n , t h e

Am29LV400B features unlock bypass programming

and in-system sector protection/unprotection.

The standard device offers access times of 55, 70, 90

and 120 ns, allowing high speed microprocessors to

operate without wait states. To eliminate bus conten-

tion the device has separate chip enable (CE#), write

enable (WE#) and output enable (OE#) controls.

The device requires only a

single 3.0 volt power sup-

ply

for both read and write functions. Internally gener-

ated and regulated voltages are provided for the

program and erase operations.

The device is entirely command set compatible with

the

JEDEC single-power-supply Flash standard.

Commands are written to the command register using

standard microprocessor write timings. Register con-

tents serve as input to an internal state-machine that

controls the erase and programming circuitry. Write

cycles also internally latch addresses and data

needed for the programming and erase operations.

Reading data out of the device is similar to reading

from other Flash or EPROM devices.

Device programming occurs by executing the program

command sequence. This initiates the

Embedded

Program

algorithm—an internal algorithm that auto-

matically times the program pulse widths and verifies

proper cell margin. The

Unlock Bypass

mode facili-

tates faster programming times by requiring only two

write cycles to program data instead of four.

Device erasure occurs by executing the erase com-

mand sequence. This initiates the

Embedded Erase

algorithm—an internal algorithm that automatically

pre-programs the array (if it is not already programmed)

before executing the erase operation. During erase,

the device automatically times the erase pulse widths

and verifies proper cell margin.

The host system can detect whether a program or

erase operation is complete by observing the RY/BY#

pin, or by reading the DQ7 (Data# Polling) and DQ6

(toggle)

status bits.

After a program or erase cycle

has been completed, the device is ready to read array

data or accept another command.

The

sector erase architecture

allows memory sec-

tors to be erased and reprogrammed without affecting

the data contents of other sectors. The device is fully

erased when shipped from the factory.

Hardware data protection

measures include a low

detector that automatically inhibits write opera-

tions during power transitions. The

hardware sector

protection

feature disables both program and erase

operations in any combination of the sectors of mem-

ory. This can be achieved in-system or via program-

ming equipment.

The

Erase Suspend

feature enables the user to put

erase on hold for any period of time to read data from,

or program data to, any sector that is not selected for

erasure. True background erase can thus be achieved.

The

hardware RESET# pin

terminates any operation

in progress and resets the internal state machine to

reading array data. The RESET# pin may be tied to

the system reset circuitry. A system reset would thus

also reset the device, enabling the system micropro-

cessor to read the boot-up firmware from the Flash

memory.

The device offers two power-saving features. When

addresses have been stable for a specified amount of

time, the device enters the

automatic sleep mode.

The system can also place the device into the

standby mode.

Power consumption is greatly re-

duced in both these modes.

AMD’s Flash technology combines years of Flash

memory manufacturing experience to produce the

highest levels of quality, reliability and cost effectiveness.

The device electrically erases all bits within a sector si-

multaneously via Fowler-Nordheim tunneling. The data is

programmed using hot electron injection.

Am29LV400B

21523D4 December 4, 2006

D A T A

S H E E T

TABLE OF CONTENTS

Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 4

Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . 5

Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . 6

Special Handling Instructions for (FBGA) ......................................7

Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 8

Device Bus Operations . . . . . . . . . . . . . . . . . . . . . 9

Table 1. Am29LV400B Device Bus Operations ......................................9

Table 6. Write Operation Status ........................................................... 23

Absolute Maximum Ratings. . . . . . . . . . . . . . . . . 24

Figure 7. Maximum Negative Overshoot Waveform............................. 24

Figure 8. Maximum Positive Overshoot Waveform .............................. 24

DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 25

Figure 9. I

CC1

Current vs. Time (Showing Active and Automatic

Sleep Currents)..................................................................................... 26

Figure 10. Typical I

CC1

vs. Frequency................................................... 26

Word/Byte Configuration ................................................................9

Requirements for Reading Array Data ...........................................9

Writing Commands/Command Sequences .................................. 10

Program and Erase Operation Status .......................................... 10

Standby Mode .............................................................................. 10

Automatic Sleep Mode ................................................................. 10

RESET#: Hardware Reset Pin ..................................................... 10

Output Disable Mode ................................................................... 11

Table 2. Am29LV400BT Top Boot Sector Address Table .....................11

Table 3. Am29LV400BB Bottom Boot Sector Address Table ...............11

Test Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Figure 11. Test Setup ........................................................................... 27

Table 7. Test Specifications .................................................................. 27

Figure 12. Input Waveforms and Measurement Levels ........................ 27

AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 28

Read Operations .......................................................................... 28

Figure 13. Read Operations Timings.................................................... 28

Hardware Reset (RESET#) .......................................................... 29

Figure 14. RESET# Timings ................................................................. 29

Autoselect Mode .......................................................................... 12

Table 4. Am29LV400B Autoselect Codes (High Voltage Method) ........12

Word/Byte Configuration (BYTE#) ............................................. 30

Figure 15. BYTE# Timings for Read Operations .................................. 30

Figure 16. BYTE# Timings for Write Operations .................................. 30

Sector Protection/Unprotection .................................................... 12

Figure 1. In-System Sector Protect/Unprotect Algorithms .................... 13

Erase/Program Operations .......................................................... 31

Figure 17. Program Operation Timings ................................................

Figure 18. Chip/Sector Erase Operation Timings .................................

Figure 19. Data# Polling Timings (During Embedded Algorithms) .......

Figure 20. Toggle Bit Timings (During Embedded Algorithms) ............

Figure 21. DQ2 vs. DQ6 .......................................................................

Figure 22. Temporary Sector Unprotect Timing Diagram.....................

Figure 23. Sector Protect/Unprotect Timing Diagram...........................

Figure 24. Alternate CE# Controlled Write Operation Timings .............

Temporary Sector Unprotect ........................................................ 14

Figure 2. Temporary Sector Unprotect Operation................................. 14

Hardware Data Protection ............................................................ 14

Low V

Write Inhibit .................................................................... 14

Write Pulse “Glitch” Protection ..................................................... 14

Logical Inhibit ............................................................................... 14

Power-Up Write Inhibit ................................................................. 14

Command Definitions . . . . . . . . . . . . . . . . . . . . . 15

Reading Array Data ...................................................................... 15

Reset Command .......................................................................... 15

Autoselect Command Sequence .................................................. 15

Word/Byte Program Command Sequence ................................... 15

Unlock Bypass Command Sequence ........................................... 16

Figure 3. Program Operation ................................................................ 16

Chip Erase Command Sequence ................................................. 16

Sector Erase Command Sequence .............................................. 17

Erase Suspend/Erase Resume Commands ................................ 17

Figure 4. Erase Operation..................................................................... 18

Table 5. Am29LV400B Command Definitions .......................................19

Write Operation Status . . . . . . . . . . . . . . . . . . . . 20

DQ7: Data# Polling ...................................................................... 20

Figure 5. Data# Polling Algorithm ......................................................... 20

RY/BY#: Ready/Busy# ................................................................. 21

DQ6: Toggle Bit I .......................................................................... 21

DQ2: Toggle Bit II ......................................................................... 21

Reading Toggle Bits DQ6/DQ2 .................................................... 21

DQ5: Exceeded Timing Limits ...................................................... 22

DQ3: Sector Erase Timer ............................................................. 22

Figure 6. Toggle Bit Algorithm............................................................... 22

Erase And Programming Performance. . . . . . . . 39

Latchup Characteristics . . . . . . . . . . . . . . . . . . . 39

TSOP And SO Pin Capacitance . . . . . . . . . . . . . 39

BGA Ball Capacitance . . . . . . . . . . . . . . . . . . . . . 40

Data Retention . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

TS 048—48-Pin Standard TSOP ................................................. 41

TSR048—48-Pin Reverse TSOP ................................................. 42

FBA048—48-ball Fine-Pitch Ball Grid Array (FBGA)

6 x 8 mm package ........................................................................ 43

SO 044—44-Pin Small Outline Package ..................................... 44

Revision A (January 1998) ........................................................... 45

Revision B (July 1998) ................................................................. 45

Revision B+1 (August 1998) ........................................................ 45

Revision C (January 1999) ........................................................... 45

Revision C+1 (July 2, 1999) ......................................................... 45

Revision D (January 3, 1999) ....................................................... 45

Revision D+1 (November 8, 2000) ............................................... 45

Revision D+2 (October 30, 2003) ................................................ 45

Revision D+3 (December 13, 2005) ............................................. 45

Revision D4 (December 4, 2006) ................................................. 45

December 4, 2006 21523D4

Am29LV400B