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ADVANCE INFORMATION

Am29LV640GH/L

64 Megabit (8 M x 8-Bit/4 M x 16-Bit) CMOS 3.0 Volt-only

Uniform Sector Flash Memory with VersatileI/O Control

DISTINCTIVE CHARACTERISTICS

ARCHITECTURAL ADVANTAGES

■

Single power supply operation

— 2.7 to 3.6 volt read, erase, and program operations

■

SecSi (Secured Silicon) Sector region

— 256-byte sector for permanent, secure identification

through an 8-word random Electronic Serial Number

— May be programmed and locked at the factory or by

the customer

— Accessible through a command sequence

■

VersatileI/O control

— Device generates data output voltages and tolerates

data input voltages as determined by the voltage on

the V

■

Manufactured on 0.17 µm process technology

■

Flexible sector architecture

— One hundred twenty-eight 64 Kbyte sectors

■

Compatibility with JEDEC standards

— Pinout and software compatible with single-power

supply Flash standard

■

Package options

— 56-pin TSOP

— 64-ball Fortified BGA

■

Minimum 1 million erase cycle guarantee per sector

■

20-year data retention at 125°C

■

Program and erase performance (V

not applied to

the ACC input pin)

— Byte program time: 5 µs typical

— Word program time: 7 µs typical

— Sector erase time: 0.6 s typical for each 64 Kbyte

sector

SOFTWARE AND HARDWARE FEATURES

■

Hardware features

—

Ready/Busy# output (RY/BY#):

indicates program or

erase cycle completion

—

Hardware reset input (RESET#):

resets device for

new operation

— WP# input protects first or last 64 Kbyte sector

regardless of sector protection settings

—

ACC input:

Accelerates programming time for higher

throughput during system production

■

Software features

—

Program Suspend & Resume:

read other sectors

before programming operation is completed

—

Sector Group Protection:

-level method of

preventing program or erase operations within a

sector

—

Temporary Sector Group Unprotect:

-level method

of changing in previously locked sectors

—

CFI (Common Flash Interface) compliant:

allows host

system to identify and accommodate multiple flash

devices

—

Erase Suspend/Erase Resume:

read/program other

sectors before an erase operation is complete

—

Data# Polling

and

toggle bits

provide erase and

programming operation status

—

Unlock Bypass Program

command reduces overall

multiple-word programming time

PERFORMANCE CHARCTERISTICS

■

High performance

— Access time ratings as fast as 70 ns

■

Ultra low power consumption (typical values at 3.0 V,

5 MHz)

— 9 mA typical active read current

— 26 mA typical erase/program current

— 200 nA typical standby mode current

This Data Sheet states AMD’s current technological specifications regarding the Products described herein. This Data Sheet may be revised by subsequent versions or

modifications due to changes in technical specifications. This document contains information on a product under development at Advanced Micro Devices. The

information is intended to help you evaluate this product. Do not design in this product without contacting the factory. AMSD reserves the right to change or discontinue

work on this proposed product without notice.

Publication#

25293

Rev:

Amendment/1

Issue Date:

August 28, 2002

Refer to AMD’s Website (www.amd.com) for the latest information.

A D V A N C E

I N F O R M A T I O N

GENERAL DESCRIPTION

The Am29LV640GH/L is a 64 Mbit, 3.0 volt (2.7 V to

3.6 V) single power supply flash memory devices or-

ganized as 4,194,304 words or 8,388,608 bytes. Data

app ea rs on DQ 15 –DQ 0 in wo r d mod e and o n

DQ7–DQ0 in byte mode. The device is designed to be

programmed in-system with the standard system 3.0

volt V

supply. A 12.0 volt V

is not required for pro-

gram or erase operations. The device can also be pro-

grammed in standard EPROM programmers.

Access times of 70, 90, and 100 ns are available for

applications where V

≥

. Access times of 90 and

100 ns are available for applications where V

< V

The device is offered in 56-pin TSOP and 64-ball Forti-

fied BGA packages. To eliminate bus contention each

device has separate chip enable (CE#), write enable

(WE#) and output enable (OE#) controls.

Each device requires only a

single 3.0 volt power

supply

(2.7 V to 3.6 V) for both read and write func-

tions. Internally generated and regulated voltages are

provided for the program and erase operations.

The device is entirely command set compatible with

the

JEDEC single-power-supply Flash standard.

Commands are written to the command register using

standard microprocessor write timing. Register con-

tents serve as inputs to an internal state-machine that

controls the erase and programming circuitry. Write

cycles also internally latch addresses and data

needed for the programming and erase operations.

Reading data out of the device is similar to reading

from other Flash or EPROM devices.

Device programming occurs by executing the program

command sequence. This initiates the

Embedded

Program

algorithm—an internal algorithm that auto-

matically times the program pulse widths and verifies

proper cell margin. The Unlock Bypass mode facili-

tates faster programming times by requiring only two

write cycles to program data instead of four.

Device erasure occurs by executing the erase com-

mand sequence. This initiates the

Embedded Erase

algorithm—an internal algorithm that automatically

preprograms the array (if it is not already pro-

grammed) before executing the erase operation. Dur-

ing erase, the device automatically times the erase

pulse widths and verifies proper cell margin.

The

VersatileI/O™

) control allows the host sys-

tem to set the voltage levels that the device generates

at its data outputs and the voltages tolerated at its

data inputs to the same voltage level that is asserted

on the V

pin. This allows the device to operate in 1.8

V or 3 V system environment as required.

The host system can detect whether a program or

erase operation is complete by observing the RY/BY#

pin, by reading the DQ7 (Data# Polling), or DQ6 (tog-

gle)

status bits.

After a program or erase cycle has

been completed, the device is ready to read array data

or accept another command.

The

sector erase architecture

allows memory sec-

tors to be erased and reprogrammed without affecting

the data contents of other sectors. The device is fully

erased when shipped from the factory.

Hardware data protection

measures include a low

detector that automatically inhibits write opera-

tions during power transitions. The hardware sector

protection feature disables both program and erase

operations in any combination of sectors of memory.

This can be achieved in-system or via programming

equipment.

The

Erase Suspend/Erase Resume

feature enables

the user to put erase on hold for any period of time to

read data from, or program data to, any sector that is

not selected for erasure. True background erase can

thus be achieved. The

Program Suspend/Program

Resume

feature enables the host system to pause a

program operation in a given sector to read any other

sector and then complete the program operation.

The

hardware RESET# pin

terminates any operation

in progress and resets the internal state machine to

reading array data. The RESET# pin may be tied to

the system reset circuitry. A system reset would thus

also reset the device, enabling the system micropro-

cessor to read boot-up firmware from the Flash mem-

ory device.

The device offers a

standby mode

as a power-saving

feature. Once the system places the device into the

standby mode power consumption is greatly reduced.

The

SecSi (Secured Silicon) Sector

provides an

minimum 128-word area for code or data that can be

permanently protected. Once this sector is protected,

no further programming or erasing within the sector

can occur.

The

Write Protect (WP#)

feature protects the first or

last sector by asserting a logic low on the WP# pin.

The protected sector will still be protected even during

accelerated programming.

The

accelerated program (ACC)

feature allows the

system to program the device at a much faster rate.

When ACC is pulled high to V

, the device enters the

Unlock Bypass mode, enabling the user to reduce the

time needed to do the program operation. This feature

is intended to increase factory throughput during sys-

tem production, but may also be used in the field if de-

sired.

AMD’s Flash technology combines years of Flash

memory manufacturing experience to produce the

highest levels of quality, reliability and cost effective-

ness. The device electrically erases all bits within a

sector simultaneously via Fowler-Nordheim tunnelling.

The data is programmed using hot electron injection.

August 28, 2002

Am29LV640GH/L

A D V A N C E

I N F O R M A T I O N

TABLE OF CONTENTS

Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 4

Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . . 5

Special Package Handling Instructions .................................... 6

Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 8

Device Bus Operations . . . . . . . . . . . . . . . . . . . . . . 9

Table 1. Device Bus Operations .......................................................9

Figure 5. Data# Polling Algorithm .................................................. 28

RY/BY#: Ready/Busy# ............................................................ 29

DQ6: Toggle Bit I .................................................................... 29

Figure 6. Toggle Bit Algorithm........................................................ 29

DQ2: Toggle Bit II ................................................................... 30

Reading Toggle Bits DQ6/DQ2 ............................................... 30

DQ5: Exceeded Timing Limits ................................................ 30

DQ3: Sector Erase Timer ....................................................... 30

Table 11. Write Operation Status ................................................... 31

VersatileI/O (V

) Control ...................................................... 9

Word/Byte Configuration .......................................................... 9

Requirements for Reading Array Data ................................... 10

Writing Commands/Command Sequences ............................ 10

Accelerated Program Operation ......................................................10

Autoselect Functions .......................................................................10

Absolute Maximum Ratings . . . . . . . . . . . . . . . . 32

Figure 7. Maximum Negative Overshoot Waveform ..................... 32

Figure 8. Maximum Positive Overshoot Waveform....................... 32

Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . 32

DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 33

Figure 9. I

CC1

Current vs. Time (Showing

Active and Automatic Sleep Currents) ........................................... 34

Figure 10. Typical I

CC1

vs. Frequency ............................................ 34

Standby Mode ........................................................................ 10

Automatic Sleep Mode ........................................................... 10

RESET#: Hardware Reset Pin ............................................... 10

Output Disable Mode .............................................................. 11

Table 2. Sector Address Table ........................................................11

Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Figure 11. Test Setup.................................................................... 35

Table 12. Test Specifications ......................................................... 35

Autoselect Mode ..................................................................... 15

Table 3. Autoselect Codes, (High Voltage Method) ......................15

Key to Switching Waveforms. . . . . . . . . . . . . . . . 35

Figure 12. Input Waveforms and

Measurement Levels...................................................................... 35

Sector Group Protection and Unprotection ............................. 16

Table 4. Sector Group Protection/Unprotection Address Table .....16

Write Protect (WP#) ................................................................ 17

Temporary Sector Group Unprotect ....................................... 17

Figure 1. Temporary Sector Group Unprotect Operation................ 17

Figure 2. In-System Sector Group Protect/Unprotect Algorithms ... 18

AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 36

Read-Only Operations ........................................................... 36

Figure 13. Read Operation Timings ............................................... 36

Hardware Reset (RESET#) .................................................... 37

Figure 14. Reset Timings............................................................... 37

SecSi (Secured Silicon) Sector Flash Memory Region ....... 19

Table 5. SecSi Sector Contents ......................................................19

Word/Byte Configuration (BYTE#) .......................................... 38

Figure 15. BYTE# Timings for Read Operations............................ 38

Figure 16. BYTE# Timings for Write Operations............................ 38

Hardware Data Protection ...................................................... 19

Low VCC Write Inhibit .....................................................................20

Write Pulse “Glitch” Protection ........................................................20

Logical Inhibit ..................................................................................20

Power-Up Write Inhibit ....................................................................20

Erase and Program Operations .............................................. 39

Figure 17. Program Operation Timings..........................................

Figure 18. Accelerated Program Timing Diagram..........................

Figure 19. Chip/Sector Erase Operation Timings ..........................

Figure 20. Data# Polling Timings

(During Embedded Algorithms)......................................................

Figure 21. Toggle Bit Timings

(During Embedded Algorithms)......................................................

Figure 22. DQ2 vs. DQ6.................................................................

Common Flash Memory Interface (CFI) . . . . . . . 20

Table 6. CFI Query Identification String ..........................................

Table 7. System Interface String.....................................................

Table 8. Device Geometry Definition ..............................................

Table 9. Primary Vendor-Specific Extended Query ........................

Command Definitions . . . . . . . . . . . . . . . . . . . . . 22

Reading Array Data ................................................................ 22

Reset Command ..................................................................... 23

Autoselect Command Sequence ............................................ 23

Enter SecSi Sector/Exit SecSi Sector Command Sequence .. 23

Word Program Command Sequence ..................................... 23

Unlock Bypass Command Sequence ..............................................24

Figure 3. Program Operation .......................................................... 24

Temporary Sector Unprotect .................................................. 44

Figure 23. Temporary Sector Group Unprotect Timing Diagram ... 44

Figure 24. Sector Group Protect and Unprotect Timing Diagram .. 45

Alternate CE# Controlled Erase and Program Operations ..... 46

Figure 25. Alternate CE# Controlled Write

(Erase/Program) Operation Timings .............................................. 47

Chip Erase Command Sequence ........................................... 24

Sector Erase Command Sequence ........................................ 25

Erase Suspend/Erase Resume Commands ........................... 25

Program Suspend/Program Resume Commands .................. 26

Figure 4. Erase Operation............................................................... 26

Command Definitions ............................................................. 27

Table 10. Command Definitions...................................................... 27

Write Operation Status . . . . . . . . . . . . . . . . . . . . . 28

DQ7: Data# Polling ................................................................. 28

Erase And Programming Performance . . . . . . . 48

Latchup Characteristics . . . . . . . . . . . . . . . . . . . . 48

TSOP Pin Capacitance . . . . . . . . . . . . . . . . . . . . . 48

Data Retention. . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 49

LAA064—64-Ball Fortified Ball Grid Array (Fortified

BGA) 13 x 11 mm package ..................................................... 49

TS 056/TSR056—56-Pin Standard/Reverse Thin Small Outline

Package (TSOP) ..................................................................... 50

Draft Revision Summary . . . . . . . . . . . . . . . . . . . 51

August 28, 2002

Am29LV640GH/L

A D V A N C E

I N F O R M A T I O N

PRODUCT SELECTOR GUIDE

Family Part Number

Speed Option

Max Access Time (ns)

CE# Access (ns)

OE# Access (ns)

Note:

See “AC Characteristics” for full specifications.

Standard Voltage Range: V

= 2.7–3.6 V

Am29LV640GH/L

100

BLOCK DIAGRAM

RY/BY#

RESET#

Erase Voltage

Generator

Input/Output

Buffers

Sector Switches

DQ15

–

DQ0

WE#

BYTE#

WP#/ACC

State

Control

Command

PGM Voltage

Generator

Chip Enable

Output Enable

Logic

STB

Data

Latch

CE#

OE#

STB

Detector

Timer

Address Latch

Y-Decoder

Y-Gating

X-Decoder

Cell Matrix

A21–A0

Am29LV640GH/L

August 28, 2002

A D V A N C E

I N F O R M A T I O N

CONNECTION DIAGRAMS

A15

A14

A13

A12

A11

A10

A19

A20

WE#

RESET#

A21

WP#/ACC

RY/BY#

A18

A17

56-Pin Standard TSOP

A16

BYTE#

DQ15/A-1

DQ7

DQ14

DQ6

DQ13

DQ5

DQ12

DQ4

DQ11

DQ3

DQ10

DQ2

DQ9

DQ1

DQ8

DQ0

OE#

CE#

A16

BYTE#

DQ15/A-1

DQ7

DQ14

DQ6

DQ13

DQ5

DQ12

DQ4

DQ11

DQ3

DQ10

DQ2

DQ9

DQ1

DQ8

DQ0

OE#

CE#

56-Pin Reverse TSOP

A15

A14

A13

A12

A11

A10

A19

A20

WE#

RESET#

A21

WP#/ACC

RY/BY#

A18

A17

August 28, 2002

Am29LV640GH/L