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AM29LV641ML120FI

64 Megabit (4 M x 16-Bit) MirrorBit⑩ 3.0 Volt-only Uniform Sector Flash Memory with VersatileI/O⑩ Control

器件类别:存储    存储   

厂商名称:AMD(超微)

厂商官网:http://www.amd.com

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器件参数
参数名称
属性值
是否Rohs认证
不符合
厂商名称
AMD(超微)
零件包装代码
TSOP1
包装说明
REVERSE, MO-142BDD, TSOP-48
针数
48
Reach Compliance Code
unknow
ECCN代码
3A991.B.1.A
最长访问时间
120 ns
命令用户界面
YES
通用闪存接口
YES
数据轮询
YES
JESD-30 代码
R-PDSO-G48
JESD-609代码
e0
长度
18.4 mm
内存密度
67108864 bi
内存集成电路类型
FLASH
内存宽度
16
功能数量
1
部门数/规模
128
端子数量
48
字数
4194304 words
字数代码
4000000
工作模式
ASYNCHRONOUS
最高工作温度
85 °C
最低工作温度
-40 °C
组织
4MX16
封装主体材料
PLASTIC/EPOXY
封装代码
TSOP1-R
封装等效代码
TSSOP48,.8,20
封装形状
RECTANGULAR
封装形式
SMALL OUTLINE, THIN PROFILE
页面大小
4 words
并行/串行
PARALLEL
电源
1.8/3.3,3/3.3 V
编程电压
3 V
认证状态
Not Qualified
反向引出线
YES
座面最大高度
1.2 mm
部门规模
32K
最大待机电流
0.000005 A
最大压摆率
0.06 mA
最大供电电压 (Vsup)
3.6 V
最小供电电压 (Vsup)
2.7 V
标称供电电压 (Vsup)
3 V
表面贴装
YES
技术
CMOS
温度等级
INDUSTRIAL
端子面层
Tin/Lead (Sn/Pb)
端子形式
GULL WING
端子节距
0.5 mm
端子位置
DUAL
切换位
YES
类型
NOR TYPE
宽度
12 mm
文档预览
Am29LV641MH/L
Data Sheet
RETIRED
PRODUCT
This product has been retired and is not available for designs. For new and current designs,
S29GL064A supersedes Am29LV641M H/L and is the factory-recommended migration path. Please
refer to the S29GL064A datasheet for specifications and ordering information. Availability of this
document is retained for reference and historical purposes only.
April 2005
The following document specifies Spansion memory products that are now offered by both Advanced
Micro Devices and Fujitsu. Although the document is marked with the name of the company that
originally developed the specification, these products will be offered to customers of both AMD and
Fujitsu.
Continuity of Specifications
There is no change to this datasheet as a result of offering the device as a Spansion product. Any
changes that have been made are the result of normal datasheet improvement and are noted in the
document revision summary, where supported. Future routine revisions will occur when appro-
priate, and changes will be noted in a revision summary.
For More Information
Please contact your local AMD or Fujitsu sales office for additional information about Spansion
memory solutions.
Publication Number
25261
Revision
B
Amendment
+10
Issue Date
December 21, 2005
THIS PAGE LEFT INTENTIONALLY BLANK.
Am29LV641MH/L
64 Megabit (4 M x 16-Bit) MirrorBit™ 3.0 Volt-only
Uniform Sector Flash Memory with VersatileI/O™ Control
DISTINCTIVE CHARACTERISTICS
information. Availability of this document is retained for reference and historical purposes only.
Please refer to the S29GL064A datasheet for specifications and ordering
ARCHITECTURAL ADVANTAGES
Single power supply operation
— 3 V for read, erase, and program operations
VersatileI/O™ control
— Device generates data output voltages and tolerates
data input voltages on CE# and the DQ inputs/outputs
as determined by the voltage on the V
IO
pin; operates
from 1.65 to 3.6 V
Manufactured on 0.23 µm MirrorBit process
technology
SecSi™ (Secured Silicon) Sector region
— 128-word sector for permanent, secure identification
through an 8-word random Electronic Serial Number,
accessible through a command sequence
— May be programmed and locked at the factory or by
the customer
Flexible sector architecture
— One hundred twenty-eight 32 Kword sectors
Compatibility with JEDEC standards
— Provides pinout and software compatibility for
single-power supply flash, and superior inadvertent
write protection
Minimum 100,000 erase cycle guarantee per sector
20-year data retention at 125°C
PERFORMANCE CHARACTERISTICS
High performance
— 90 ns access time
— 25 ns page read times
— 0.5 s typical sector erase time
— 22 µs typical effective write buffer word programming
time: 16-word write buffer reduces overall
programming time for multiple-word updates
— 4-word page read buffer
— 16-word write buffer
This product has been retired and is not available for designs. For new and current designs, S29GL064A supersedes Am29LV641M H/L and is the factory-recommended migration path.
Low power consumption (typical values at 3.0 V, 5
MHz)
— 30 mA typical active read current
— 50 mA typical erase/program current
— 1 µA typical standby mode current
Package options
— 48-pin TSOP
SOFTWARE & HARDWARE FEATURES
Software features
— Program Suspend & Resume: read other sectors
before programming operation is completed
— Erase Suspend & Resume: read/program other
sectors before an erase operation is completed
— Data# polling & toggle bits provide status
— Unlock Bypass Program command reduces overall
multiple-word programming time
— CFI (Common Flash Interface) compliant: allows host
system to identify and accommodate multiple flash
devices
Hardware features
— Sector Group Protection: hardware-level method of
preventing write operations within a sector group
— Temporary Sector Unprotect: V
ID
-level method of
changing code in locked sectors
— ACC (high voltage) input accelerates programming
time for higher throughput during system production
— Write Protect input (WP#) protects first or last sector
regardless of sector protection settings
— Hardware reset input (RESET#) resets device
This Data Sheet states AMD’s current technical specifications regarding the Products described herein. This Data
Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
Publication#
25261
Amendment/+10
Rev:
B
Issue Date:
December 21, 2005
Refer to AMD’s Website (www.amd.com) for the latest information.
D A T A S H E E T
GENERAL DESCRIPTION
The Am29LV641MH/L is a 64 Mbit, 3.0 volt single
power supply flash memory devices organized as
4,194,304 words. The devices have a 16-bit wide data
bus, and can be programmed either in the host system
or in standard EPROM programmers.
An access time of 90, 100, 110, or 120 ns is available.
Note that each access time has a specific operating
voltage range (V
CC
) and an I/O voltage range (V
IO
), as
specified in the
Product Selector Guide
and the
Order-
ing Information
sections. The device is offered in a
48-pin TSOP package. Each device has separate chip
enable (CE#), write enable (WE#) and output enable
(OE#) controls.
Each device requires only a
single 3.0 volt power
supply
for both read and write functions. In addition to
a V
CC
input, a high-voltage
accelerated program
(ACC)
input provides shorter programming times
through increased current. This feature is intended to
facilitate factory throughput during system production,
but may also be used in the field if desired.
The device is entirely command set compatible with
the
JEDEC single-power-supply Flash standard.
Commands are written to the device using standard
microprocessor write timing. Write cycles also inter-
nally latch addresses and data needed for the pro-
gramming and erase operations.
The
sector erase architecture
allows memory sec-
tors to be erased and reprogrammed without affecting
the data contents of other sectors. The device is fully
erased when shipped from the factory.
Device programming and erasure are initiated through
command sequences. Once a program or erase oper-
ation has begun, the host system need only poll the
DQ7 (Data# Polling) or DQ6 (toggle)
status bits
to de-
termine whether the operation is complete. To facilitate
programming, an
Unlock Bypass
mode reduces com-
mand sequence overhead by requiring only two write
cycles to program data instead of four.
The
VersatileI/O™
(V
IO
) control allows the host sys-
tem to set the voltage levels that the device generates
and tolerates on the CE# control input and DQ I/Os to
the same voltage level that is asserted on the V
IO
pin.
Refer to the
Ordering Information
section for valid V
IO
options.
Hardware data protection
measures include a low
V
CC
detector that automatically inhibits write opera-
tions during power transitions. The hardware sector
protection feature disables both program and erase
operations in any combination of sectors of memory.
This can be achieved in-system or via programming
equipment.
The
Erase Suspend/Erase Resume
feature allows
the host system to pause an erase operation in a given
sector to read or program any other sector and then
complete the erase operation. The
Program Sus-
pend/Program Resume
feature enables the host sys-
tem to pause a program operation in a given sector to
read any other sector and then complete the program
operation.
The
hardware RESET# pin
terminates any operation
in progress and resets the device, after which it is then
ready for a new operation. The RESET# pin may be
tied to the system reset circuitry. A system reset would
thus also reset the device, enabling the host system to
read boot-up firmware from the Flash memory device.
The device reduces power consumption in the
standby mode
when it detects specific voltage levels
on CE# and RESET#, or when addresses have been
stable for a specified period of time.
The
SecSi™ (Secured Silicon) Sector
provides a
128-word area for code or data that can be perma-
nently protected. Once this sector is protected, no fur-
ther changes within the sector can occur.
The
Write Protect (WP#)
feature protects the first or
last sector by asserting a logic low on the WP# pin.
The protected sector will still be protected even during
accelerated programming.
AMD MirrorBit flash technology combines years of
Flash memory manufacturing experience to produce
the highest levels of quality, reliability and cost effec-
tiveness. The device electrically erases all bits within a
sector simultaneously via hot-hole assisted erase. The
data is programmed using hot electron injection.
2
Am29LV641MH/L
December 21, 2005
D A T A S H E E T
MIRRORBIT 64 MBIT DEVICE FAMILY
Device
LV065MU
LV640MT/B
LV640MH/L
LV641MH/L
LV640MU
Bus
x8
x8/x16
x8/x16
x16
x16
Sector Architecture
Uniform (64K-byte)
Boot (8x8K-byte
@ top & bottom)
Uniform (64K-byte)
Uniform (32K-word)
Uniform (32K-word)
Packages
48-pin TSOP (std. & rev. pinout),
63-ball FBGA
48-pin TSOP, 63-ball Fine-pitch BGA,
64-ball Fortified BGA
56-pin TSOP (std. & rev. pinout),
64 Fortified BGA
48-pin TSOP (std. & rev. pinout)
63-ball Fine-pitch BGA,
64 Ball Fortified BGA
V
IO
Yes
No
Yes
Yes
Yes
RY/BY#
Yes
Yes
Yes
No
Yes
WP#, ACC
ACC only
WP#/ACC pin
WP#/ACC pin
Separate WP#
and ACC pins
ACC only
WP# Protection
No WP#
2 x 8 Kbyte top
or bottom
1 x 64 Kbyte
high or low
1 x 32 Kword top
or bottom
No WP#
RELATED DOCUMENTS
To download related documents, click on the following
links or go to www.amd.com
Flash Memory
Prod-
uct Information
MirrorBit
Flash Information
Tech-
nical Documentation.
MirrorBit™ Flash Memory Write Buffer Programming
and Page Buffer Read
Implementing a Common Layout for AMD MirrorBit
and Intel StrataFlash Memory Devices
AMD MirrorBit™ White Paper
Migrating from Single-byte to Three-byte Device IDs
December 21, 2005
Am29LV641MH/L
3
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