PRELIMINARY
Am29LV800T/Am29LV800B
8 Megabit (1,048,576 x 8-Bit/524,288 x 16-Bit)
CMOS 3.0 Volt-only, Sectored Flash Memory
DISTINCTIVE CHARACTERISTICS
s
Single power supply operation
— Extended voltage range: 2.7 to 3.6 volt read and
write operations for battery-powered
applications
— Standard voltage range: 3.0 to 3.6 volt read and
write operations and for compatibility with high
performance 3.3 volt microprocessors
s
High performance
— Extended voltage range: access times as fast as
100 ns
— Standard voltage range: access times as fast as
90 ns
s
Ultra low power consumption
— Automatic Sleep Mode: 200 nA typical
— Standby mode: 200 nA typical
— Read mode: 2 mA/MHz typical
— Program/erase mode: 20 mA typical
s
Flexible sector architecture
— One 16 Kbyte, two 8 Kbyte, one 32 Kbyte, and
fifteen 64 Kbyte sectors (byte mode)
— One 8 Kword, two 4 Kword, one 16 Kword, and
fifteen 32 Kword sectors (word mode)
— Supports control code and data storage on a
single device
— Sector Protection features:
A hardware method of locking a sector to
prevent any program or erase operations within
that sector
Temporary Sector Unprotect feature allows code
changes in previously locked sectors
s
Top or bottom boot block configurations
available
s
Embedded Algorithms
— Embedded Erase algorithms automatically
preprogram and erase the entire chip or any
combination of designated sectors
— Embedded Program algorithms automatically
write and verify bytes or words at specified
addresses
s
Minimum 100,000 write cycle guarantee per
sector
s
Package options
— 48-pin TSOP
— 44-pin SO
s
Compatibility with JEDEC standards
— Pinout and software compatible with single-
power supply Flash
— Superior inadvertent write protection
s
Data Polling and toggle bits
— Provides a software method of detecting
program or erase operation completion
s
Ready/Busy pin (RY/BY)
— Provides a hardware method of detecting
program or erase cycle completion
s
Erase suspend/resume commands
— Suspends the erase operation to read data from
or program data to another sector, then resumes
the erase operation
s
Hardware reset pin (RESET)
— Hardware method to reset the device to the read
mode
This document contains information on a product under development at Advanced Micro Devices. The information
is intended to help you evaluate this product. AMD reserves the right to change or discontinue work on this proposed
product without notice.
Publication#
20478
Rev:
D
Amendment/0
Issue Date:
November 1997
Refer to AMD’s Website (www.amd.com) for the latest information.
P R E L I M I N A R Y
GENERAL DESCRIPTION
The Am29LV800 is an 8 Mbit, 3.0 Volt-only Flash mem-
ory organized as 1 Mbyte of 8 bits each or 512K words
of 16 bits each. For flexible erase and program capabil-
ity, the 8 Mbits of data is divided into 19 sectors of one
16 Kbyte, two 8 Kbyte, one 32 Kbyte, and fifteen 64
Kbytes. The x8 data appears on DQ0–DQ7; the x16
data appears on DQ0–DQ15. The Am29LV800 is of-
fered in 44-pin SO and 48-pin TSOP packages. This
device is designed to be programmed in-system with
the standard system 3.0 Volt V
CC
supply. The device
can also be reprogrammed in standard EPROM
programmers.
The Am29LV800 provides two levels of performance.
The first level offers access times as fast as 100 ns with
a V
CC
range as low as 2.7 volts, which is optimal for
battery powered applications. The second level offers a
90 ns access time, optimizing performance in systems
where the power supply is in the regulated range of 3.0
to 3.6 volts. To eliminate bus contention, the device has
separate chip enable (CE), write enable (WE), and
output enable (OE) controls.
The Am29LV800 is entirely command set compatible
with the JEDEC single-power-supply Flash standard.
Commands are written to the command register using
standard microprocessor write timings. Register con-
tents serve as input to an internal state-machine which
controls the erase and programming circuitry. Write cy-
cles also internally latch addresses and data needed
for the programming and erase operations. Reading
data out of the device is similar to reading from other
Flash or EPROM devices.
The Am29LV800 is programmed by executing the pro-
gram command sequence. This will invoke the Embed-
ded Program Algorithm which is an internal algorithm
that automatically times the program pulse widths and
verifies proper cell margin. Erase is accomplished by
executing the erase command sequence. This will in-
voke the Embedded Erase Algorithm which is an inter-
nal algorithm that automatically pre-programs the array
if it is not already programmed before executing the
erase operation. During erase, the device automatically
times the erase pulse widths and verifies proper cell
margin.
This device also features a sector erase architecture.
This allows for sectors of memory to be erased and re-
programmed without affecting the data contents of
other sectors. A sector is typically erased and verified
within 1.0 second. The Am29LV800 is fully erased
when shipped from the factory.
The Am29LV800 device also features hardware sector
protection. This feature will disable both program and
erase operations in any combination of nineteen sec-
tors of memory.
AMD has implemented an Erase Suspend feature that
enables the user to put erase on hold for any period of
time to read data from or program data to a sector that
was not being erased. Thus, true background erase
can be achieved.
The device features single 3.0 Volt power supply oper-
ation for both read and write functions. Internally gen-
erated and regulated voltages are provided for the
program and erase operations. A low V
CC
detector au-
tomatically inhibits write operations during power tran-
sitions. The end of program or erase is detected by the
RY/BY pin. Data Polling of DQ7, or by the Toggle Bit
(DQ6). Once the end of a program or erase cycle has
been completed, the device automatically resets to the
read mode.
The Am29LV800 also has a hardware RESET pin.
When this pin is driven low, execution of any Embed-
ded Program Algorithm or Embedded Erase Algorithm
will be terminated. The internal state machine will then
be reset into the read mode. The RESET pin may be
tied to the system reset circuitry. Therefore, if a system
reset occurs during the Embedded Program Algorithm
or Embedded Erase Algorithm, the device will be auto-
matically reset to the read mode and will have errone-
ous data stored in the address locations being
operated on. These locations will need rewriting after
the Reset. Resetting the device will enable the sys-
tem’s microprocessor to read the boot-up firmware
from the Flash memory.
AMD’s Flash technology combines years of Flash
memory manufacturing experience to produce the
highest levels of quality, reliability and cost effective-
ness. The Am29LV800 memory electrically erases
all bits within a sector simultaneously via Fowler-
Nordhiem tunneling. The bytes/words are programmed
one byte/word at a time using the EPROM program-
ming mechanism of hot electron injection.
2
Am29LV800T/Am29LV800B
P R E L I M I N A R Y
Flexible Sector Architecture
s
One 8 Kword, two 4 Kwords, one 16 Kword, and
fifteen 32 Kwords sectors in word mode
s
One 16 Kbyte, two 8 Kbytes, one 32 Kbyte, and
fifteen 64 Kbyte sectors in byte mode
s
Individual-sector or multiple-sector erase capability
s
Sector protection is user definable
(x8) Address
Range
SA18
SA17
SA16
SA15
SA14
SA13
SA12
SA11
SA10
SA9
SA8
SA7
SA6
SA5
SA4
SA3
SA2
SA1
SA0
16 Kbytes
8 Kwords
8 Kbytes
4 Kwords
8 Kbytes
4 Kwords
32 Kbytes
16 Kwords
(x16) Address
Range
SA18
SA17
SA16
SA15
SA14
SA13
SA12
SA11
SA10
SA9
SA8
SA7
SA6
SA5
SA4
SA3
SA2
SA1
SA0
64 Kbytes
32 Kwords
(x8) Address
Range
F0000h-FFFFFh
(x16) Address
Range
78000h-7FFFFh
70000h-77FFFh
FC000h-FFFFFh 7E000h-7FFFFh
FA000h-FBFFFh 7D000h-7DFFFh
F8000h-F9FFFh 7C000h-7CFFFh
F0000h-F7FFFh
78000h-7BFFFh
70000h-77FFFh
64 Kbytes
E0000h-EFFFFh
32 Kwords
64 Kbytes
D0000h-DFFFFh 68000h-6FFFFh
32 Kwords
64 Kbytes
C0000h-CFFFFh 60000h-67FFFh
32 Kwords
64 Kbytes
B0000h-BFFFFh 58000h-5FFFFh
32 Kwords
64 Kbytes
A0000h-AFFFFh
32 Kwords
64 Kbytes
32 Kwords
64 Kbytes
32 Kwords
64 Kbytes
32 Kwords
64 Kbytes
32 Kwords
64 Kbytes
32 Kwords
64 Kbytes
32 Kwords
64 Kbytes
32 Kwords
64 Kbytes
32 Kwords
64 Kbytes
32 Kwords
32 Kbytes
16 Kwords
8 Kbytes
4 Kwords
8 Kbytes
4 Kwords
16 Kbytes
8 Kwords
90000h-9FFFFh
80000h-8FFFFh
70000h-7FFFFh
60000h-6FFFFh
50000h-5FFFFh
40000h-4FFFFh
30000h-3FFFFh
20000h-2FFFFh
10000h-1FFFFh
08000h-0FFFFh
06000h-07FFFh
04000h-05FFFh
00000h-03FFFh
50000h-57FFFh
48000h-4FFFFh
40000h-47FFFh
38000h-3FFFFh
30000h-37FFFh
28000h-2FFFFh
20000h-27FFFh
18000h-1FFFFh
10000h-17FFFh
08000h-0FFFFh
04000h-07FFFh
03000h-03FFFh
02000h-02FFFh
00000h-01FFFh
20478D-2
64 Kbytes
E0000h-EFFFFh
32 Kwords
64 Kbytes
D0000h-DFFFFh 68000h-6FFFFh
32 Kwords
64 Kbytes
C0000h-CFFFFh 60000h-67FFFh
32 Kwords
64 Kbytes
B0000h-BFFFFh 58000h-5FFFFh
32 Kwords
64 Kbytes
A0000h-AFFFFh
32 Kwords
64 Kbytes
32 Kwords
64 Kbytes
32 Kwords
64 Kbytes
32 Kwords
64 Kbytes
32 Kwords
64 Kbytes
32 Kwords
64 Kbytes
32 Kwords
64 Kbytes
32 Kwords
64 Kbytes
32 Kwords
64 Kbytes
32 Kwords
64 Kbytes
32 Kwords
90000h-9FFFFh
80000h-8FFFFh
70000h-7FFFFh
60000h-6FFFFh
50000h-5FFFFh
40000h-4FFFFh
30000h-3FFFFh
20000h-2FFFFh
10000h-1FFFFh
00000h-0FFFFh
50000h-57FFFh
48000h-4FFFFh
40000h-47FFFh
38000h-3FFFFh
30000h-37FFFh
28000h-2FFFFh
20000h-27FFFh
18000h-1FFFFh
10000h-17FFFh
08000h-0FFFFh
00000h-07FFFh
20478D-1
Am29LV800T Sector Architecture
Notes:
The address range is A18:A-1 if in byte mode (BYTE = V
IL
).
The address range is A18:A0 if in word mode (BYTE = V
IH
).
Am29LV800B Sector Architecture
Am29LV800T/Am29LV800B
3
P R E L I M I N A R Y
PRODUCT SELECTOR GUIDE
Family Part Number
Ordering Part Number:
V
CC
= 3.0–3.6 V
V
CC
= 2.7–3.6 V
Max access time (ns)
CE access time (ns)
OE access time (ns)
90
90
40
-90R
-100
100
100
40
-120
120
120
50
-150
150
150
55
Am29LV800T/Am29LV800B
BLOCK DIAGRAM
RY/BY
V
CC
V
SS
RESET
Sector
Switches
DQ0–DQ7
Erase Voltage
Generator
State
Control
Command
Register
Input/Output
Buffers
WE
BYTE
PGM Voltage
Generator
Chip Enable
Output Enable
Logic
STB
Data Latch
CE
OE
STB
V
CC
Detector
Timer
Address Latch
Y-Decoder
Y-Gating
X-Decoder
Cell Matrix
A0–A18
20478D-3
4
Am29LV800T/Am29LV800B
P R E L I M I N A R Y
CONNECTION DIAGRAMS
SO
RY/BY
A18
A17
A7
A6
A5
A4
A3
A2
A1
A0
CE
V
SS
OE
DQ0
DQ8
DQ1
DQ9
DQ2
DQ10
DQ3
DQ11
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
RESET
WE
A8
A9
A10
A11
A12
A13
A14
A15
A16
BYTE
V
SS
DQ15/A-1
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
V
CC
20478D-4
Am29LV800T/Am29LV800B
5
Microchip MCU
